Electronic digital logic circuitry – Interface – Supply voltage level shifting
Patent
1995-11-21
1998-03-03
Santamauro, Jon
Electronic digital logic circuitry
Interface
Supply voltage level shifting
326 68, 326 83, 327333, 327589, H03K 190175
Patent
active
057239851
ABSTRACT:
The present invention discloses methods and apparatus for implementing a clocked high voltage switch involving MOS devices. The switching is from a high voltage source typically at 21V to ground. An intermediate voltage source typically at 11V is introduced for reducing the gated breakdown voltage requirement to approximately 10V. This reduced gated breakdown voltage requirement is easily met by special layout methods applied to various transistors in the circuit. The basic layout methods include the terminating of the field implant region near the N+P junction to expose the N+ diffusion over the P substrate to increase the junction breakdown and the gated diode breakdown, and the use of short channel length to reduce the threshold voltage.
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High Voltage Regulation and Process Consideration for High-Density 5 V-Only E2PROM's , Duane H. Oto et al., IEEE Journal of Solid-State Circuits, vol. SC-18, No. 5, Oct. 1983.
Blyth Trevor
Simko Richard T.
Tran Hieu Van
Information Storage Devices, Inc.
Santamauro Jon
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