Clocked half-rail differential logic with single-rail logic

Details Clocked half-rail differential logic with single-rail logic Clocked half-rail differential logic with single-rail logic

2002-08-30

2004-04-06

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S095000, C326S113000

Reexamination Certificate

active

06717438

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to logic circuits and, more particularly, to half-rail differential logic circuits.
BACKGROUND OF THE INVENTION
With the emergence of an electronics market that stresses portability, compact size, lightweight and the capability for prolonged remote operation, a demand has arisen for low power circuits and systems. This demand has motivated circuit designers to depart from conventional circuit designs and venture into more power efficient alternatives. As part of this effort, half-rail differential logic has emerged as an important design tool for increasing power efficiency.
FIG. 1A
shows a schematic diagram of one embodiment of a clocked half-rail differential logic circuit
100
designed according to the principles of the invention set forth in patent application Ser. No. 09/927,751, entitled “Clocked Half-Rail Differential Logic”, filed Aug. 9, 2001, in the name of the present inventor, assigned to the assignee of the present invention, and incorporated herein by reference, in its entirety. As seen in
FIG. 1A
, a clock signal CLK is coupled to an input node
132
of a clock inverter
134
to yield a clock-not signal CLKBAR at output node
136
of clock inverter
134
.
As also seen in
FIG. 1A
, clocked half-rail differential logic circuit
100
includes a first supply voltage
102
coupled to a source, or first flow electrode
130
, of a PFET
101
. The signal CLKBAR is coupled to a control electrode or gate
103
of PFET
101
and a control electrode or gate
129
of an NFET
109
. A drain, or second flow electrode
104
, of PFET
101
is coupled to both a source, or first flow electrode
106
, of a PFET
105
and a source, or first flow electrode
108
, of a PFET
107
. A control electrode or gate
116
of PFET
105
is coupled to a first flow electrode
140
of NFET
109
and an OUTBAR terminal
113
. A control electrode or gate
114
of PFET
107
is coupled to a second flow electrode
138
of NFET
109
and an OUT terminal
111
. A drain, or second flow electrode
110
, of PFET
105
is coupled to OUT terminal
111
and a drain, or second flow electrode
112
, of PFET
107
is coupled to OUTBAR terminal
113
.
OUT terminal
111
is coupled to a terminal
118
of a base logic portion
123
A of a logic block
123
and OUTBAR terminal
113
is coupled to a terminal
120
of a complementary logic portion
123
B of logic block
123
. Base logic portion
123
A of logic block
123
includes any type of differential logic and/or circuitry used in the art including various logic gates, logic devices and circuits. Complementary logic portion
123
B of logic block
123
includes any type of complementary differential logic and/or circuitry used in the art including various logic gates, logic devices and circuits. As discussed in more detail below, since clocked half-rail differential logic circuit
100
was a dual rail logic circuit, requiring an output OUT
111
and a complementary output OUTBAR
113
, in the prior art, logic block
123
had to include both a base logic portion
123
A, such as an AND gate, OR gate, XOR gate, etc. and the complementary logic portion
123
B of base logic portion
123
A, such as a NAND gate, NOR gate, XNOR gate, etc. Logic block
123
also includes first and second input terminals
151
and
153
that are typically coupled to an OUT and OUTBAR terminal of a previous clocked half-rail differential logic circuit stage (not shown).
Logic block
123
also includes fourth terminal
122
coupled to a drain, or first flow electrode
124
, of an NFET
125
. A gate or control electrode
127
of NFET
125
is coupled to the signal CLK and a source, or second flow electrode
126
, of NFET
125
is coupled to a second supply voltage
128
.
A particular embodiment of a clocked half-rail differential logic circuit
100
is shown in FIG.
1
A. Those of skill in the art will recognize that clocked half-rail differential logic circuit
100
can be easily modified. For example, different transistors, i.e., first, second and third PFETs
101
,
105
and
107
or first and second NFETs
109
and
125
can be used. In particular, the NFETs and PFETS shown in
FIG. 1A
can be readily exchanged for PFETs and NFETs by reversing the polarities of the supply voltages
102
and
128
, or by other well known circuit modifications. Consequently, the clocked half-rail differential logic circuit
100
that is shown in
FIG. 1A
is simply used for illustrative purposes.
Clocked half-rail differential logic circuit
100
had two modes, or phases, of operation; a pre-charge phase and an evaluation phase. In one embodiment of a clocked half-rail differential logic circuit
100
, in the pre-charge phase, the signal CLK was low or a digital “0” and the signal CLKBAR was high or a digital “1”. Consequently, first PFET
101
and second NFET
125
were not conducting or were “off” and logic block
123
was isolated from first supply voltage
102
and second supply voltage
128
. In addition, during the pre-charge phase, first NFET
109
was conducting or was “on” and, therefore, OUT terminal
111
was shorted to OUTBAR terminal
113
. Consequently, the supply voltage to logic block
123
was approximately half the supply voltage
102
, i.e., for a first supply voltage
102
of Vdd and a second supply voltage
128
of ground, logic block
123
operated at around Vdd/2. During pre-charge, second and third PFETs
105
and
107
were typically not performing any function.
In one embodiment of a clocked half-rail differential logic circuit
100
, in the evaluation phase, the signal CLK was high or a digital “1” and the signal CLKBAR was low or a digital “0”. Consequently, first PFET
101
and second NFET
125
were conducting or were “on” and first NFET
109
was not conducting or was “off”. Consequently, depending on the particular logic in logic block
123
, either second PFET
105
, or third PFET
107
, was conducting or was “on” and the other of second PFET
105
, or third PFET
107
, was not conducting or was “off”. As a result, either OUT-terminal
111
went from approximately half first supply voltage
102
to approximately second supply voltage
128
or OUTBAR terminal
113
went from approximately half first supply voltage
102
to approximately first supply voltage
102
, i.e., for a first supply voltage
102
of Vdd and a second supply voltage
128
of ground, OUT terminal
111
went from approximately vdd/2 to zero and OUTBAR terminal
113
went from approximately Vdd/2 to Vdd.
Clocked half-rail differential logic circuits
100
marked a significant improvement over prior art half-rail logic circuits in part because clocked half-rail differential logic circuit
100
does not require the complex control circuit of prior art half-rail differential logic circuits and is therefore simpler, saves space and is more reliable than prior art half-rail differential logic circuits. As a result, clocked half-rail differential logic circuits
100
are better suited to the present electronics market that stresses portability, compact size, lightweight and the capability for prolonged remote operation. However, clocked half-rail differential logic circuit
100
has some limitations.
For instance, as noted above, since clocked half-rail differential logic circuit
100
was a dual rail logic circuit, requiring an output OUT
111
and a complementary output OUTBAR
113
, in the prior art, logic block
123
had to include both a base logic function, via base logic portion
123
A of logic block
123
, such as an AND gate, OR gate, XOR gate, etc. and the complementary logic function, via complementary logic portion
123
B of logic block
123
, such as a NAND gate, NOR gate, XNOR gate, etc.
FIG. 1B
shows one particular embodiment of a clocked half-rail differential logic circuit
100
A that includes a base logic portion
123
A that is an AND gate and a complementary logic portion
123
B that is a NAND gate. As shown in
FIG. 1B
, AND gate
123
A includes NFET
161
and NFET
163
in series. Input
151
is coupled to the control electrod

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