Clocked half-rail differential logic with sense amplifier...

Details Clocked half-rail differential logic with sense amplifier... Clocked half-rail differential logic with sense amplifier...

2002-08-23

2004-07-27

Le, Don (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S028000, C326S121000

Reexamination Certificate

active

06768343

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to logic circuits and, more particularly, to half-rail differential logic circuits.
BACKGROUND OF THE INVENTION
With the emergence of an electronics market that stresses portability, compact size, lightweight and the capability for prolonged remote operation, a demand has arisen for low power circuits and systems. This demand has motivated circuit designers to depart from conventional circuit designs and venture into more power efficient alternatives. As part of this effort, half-rail differential logic has emerged as an important design tool for increasing power efficiency.
FIG. 1
shows a schematic diagram of one embodiment of a clocked half-rail differential logic circuit
100
designed according to the principles of the invention set forth in patent application Ser. No. 09/927,751, entitled “Clocked Half-Rail Differential Logic”, filed Aug. 9, 2001, in the name of the present inventor, assigned to the assignee of the present invention, and incorporated herein by reference, in its entirety. As seen in
FIG. 1
, a clock signal CLK is coupled to an input node
132
of a clock inverter
134
to yield a clock-not signal CLKBAR at output node
136
of clock inverter
134
.
As also seen in
FIG. 1
, clocked half-rail differential logic circuit
100
includes a first supply voltage
102
coupled to a source, or first flow electrode
130
, of a PFET
101
. The signal CLKBAR is coupled to a control electrode or gate
103
of first PFET
101
and a control electrode or gate
129
of a first NFET
109
. A drain, or second flow electrode
104
, of first PFET
101
is coupled to both a source, or first flow electrode
106
, of a second PFET
105
and a source, or first flow electrode
108
, of a third PFET
107
. A control electrode or gate
116
of second PFET
105
is coupled to a first flow electrode
140
of first NFET
109
and an OUTBAR terminal
113
. A control electrode or gate
114
of third PFET
107
is coupled to a second flow electrode
138
of first NFET
109
and an OUT terminal
111
. A drain, or second flow electrode
110
, of second PFET
105
is coupled to OUT terminal
111
and a drain, or second flow electrode
112
, of third PFET
107
is coupled to OUTBAR terminal
113
.
OUT terminal
111
is coupled to a first terminal
118
of a logic network
123
and OUTBAR terminal
113
is coupled to a second terminal
120
of logic network
123
. Logic network
123
includes any type of differential logic and/or circuitry used in the art including various logic gates, logic devices and circuits. Logic network
123
also includes first and second IN terminals
151
and
153
that are typically coupled to an OUT and OUTBAR terminal of a previous clocked half-rail differential logic circuit with sense amplifier and shut-off stage (not shown).
Logic network
123
also includes third terminal
122
coupled to a drain, or first flow electrode
124
, of a second NFET
125
. A gate or control electrode
127
of second NFET
125
is coupled to the signal CLK and a source, or second flow electrode
126
, of second NFET
125
is coupled to a second supply voltage
128
.
A particular embodiment of a clocked half-rail differential logic circuit
100
is shown in FIG.
1
. Those of skill in the art will recognize that clocked half-rail differential logic circuit
100
can be easily modified. For example, different transistors, i.e., first, second and third PFETs
101
,
105
and
107
or first and second NFETs
109
and
125
can be used. In particular, the NFETs and PFETS shown in
FIG. 1
can be readily exchanged for PFETs and NFETs by reversing the polarities of the supply voltages
102
and
128
, or by other well known circuit modifications. Consequently, the clocked half-rail differential logic circuit
100
that is shown in
FIG. 1
is simply used for illustrative purposes.
Clocked half-rail differential logic circuit
100
has two modes, or phases, of operation; a pre-charge phase and an evaluation phase. In one embodiment of a clocked half-rail differential logic circuit
100
, in the pre-charge phase, the signal CLK is low or a digital “0” and the signal CLKBAR is high or a digital “1”. Consequently, first PFET
101
and second NFET
125
are not conducting or are “off” and logic network
123
is isolated from first supply voltage
102
and second supply voltage
128
. In addition, during the pre-charge phase, first NFET
109
is conducting or is “on” and, therefore, OUT terminal
111
is shorted to OUTBAR terminal
113
. Consequently, the supply voltage to logic network
123
is approximately half the supply voltage
102
, i.e., for a first supply voltage
102
of Vdd and a second supply voltage
128
of ground, logic network
123
operates at around Vdd/2. During pre-charge, second and third PFETs
105
and
107
are typically not performing any function.
In one embodiment of a clocked half-rail differential logic circuit
100
, in the evaluation phase, the signal CLK is high or a digital “1” and the signal CLKBAR is low or a digital “0”. Consequently, first PFET
101
and second NFET
125
are conducting or are “on” and first NFET
109
is not conducting or is “off”. Consequently, depending on the particular logic in logic network
123
, either second PFET
105
, or third PFET
107
, is conducting or is “on” and the other of second PFET
105
, or third PFET
107
, is not conducting or is “off”. As a result, either OUT terminal
111
goes from approximately half first supply voltage
102
to approximately second supply voltage
128
or OUTBAR terminal
113
goes from approximately half first supply voltage
102
to approximately first supply voltage
102
, i.e., for a first supply voltage
102
of Vdd and a second supply voltage
128
of ground, OUT terminal
111
goes from approximately Vdd/2 to zero and OUTBAR terminal
113
goes from approximately Vdd/2 to Vdd.
Clocked half-rail differential logic circuit
100
marked a significant improvement over prior art half-rail logic circuits in part because clocked half-rail differential logic circuit
100
does not require the complex control circuit of prior art half-rail differential logic circuits and is therefore simpler, saves space and is more reliable than prior art half-rail differential logic circuits. As a result, clocked half-rail differential logic circuits
100
are better suited to the present electronics market that stresses portability, compact size, lightweight and the capability for prolonged remote operation. However, clocked half-rail differential logic circuit
100
has some limitations.
For instance, clocked half-rail differential logic circuit
100
worked very well under conditions of a light load, for instance under conditions where fan out was less than four. However, clocked half-rail differential logic circuit
100
was less useful under conditions of a heavy load, for instance, in cases where fan out exceeded four. The shortcomings of clocked half-rail differential logic circuit
100
arose primarily because under heavy load conditions logic network
123
, and the transistors and components making up logic network
123
, had to be increased in size to act as a driver for the next stage in the cascade. This in turn meant that logic network
123
was large, slow and inefficient. The problem was further aggravated as additional clocked half-rail differential logic circuits
100
were cascaded together to form the chains commonly used in the industry. Consequently, the full potential of clocked half-rail differential logic circuit
100
was not realized and its use was narrowly limited to light load applications.
In addition during the evaluation phase, clocked half-rail differential logic circuit
100
drew excess power unnecessarily as the relevant inputs,
151
or
153
, to logic network
123
were transitioning low to shut off the path of one of the complementary OUT terminals, OUT terminal
111
or OUTBAR terminal
113
, to ground. The high OUT terminal, OUT terminal
111
or OUTBAR terminal
113
, therefore experienced a “dip” or pre-cha

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