Clocked half-rail differential logic

Details Clocked half-rail differential logic Clocked half-rail differential logic

2002-10-22

2003-09-09

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S028000, C326S083000, C326S098000, C329S350000

Reexamination Certificate

active

06617882

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to logic circuits and, more particularly, to half-rail logic circuits.
BACKGROUND OF THE INVENTION
With the emergence of an electronics market that stresses portability, compact size, lightweight and the capability for prolonged remote operation, a demand has arisen for low power circuits and systems. This demand has motivated circuit designers to depart from conventional circuit designs and venture into more power efficient alternatives. As part of this effort, half-rail differential logic has emerged as an important design tool for increasing power efficiency.
FIG. 1
shows a prior art half-rail differential logic circuit
100
A and associated prior art control circuit
100
B as was set forth in
FIG. 1
of the 1997 IEEE International Solid-State Circuits Conference Paper ISSC97/SESSION 25/PROCESSORS AND LOGIC/PAPER 25.6 (hereinafter referred to as the ISSC97 PAPER 25.6). ISSC97 PAPER 25.6 is co-authored by the Inventor of the present invention and is incorporated herein, by reference, for all purposes.
As seen in
FIG. 1
of the present invention, prior art half-rail differential logic circuit
100
A included eight transistors, PFET
101
, PFET
105
, PFET
107
, NFET
109
, NFET
115
, NFET
117
, NFET
121
, and NFET
125
. Prior art half-rail differential logic circuit
100
A also included differential logic
123
with inputs
151
and
153
, output
111
and output
113
.
As discussed below, prior art half-rail differential logic circuit
100
A also required control circuit
100
B. Control circuit
100
B included six transistors: PFET
129
; NFET
131
; NFET
133
; PFET
137
; PFET
135
and NFET
139
. Prior art control circuit
100
B also included an enable out signal (eout) at terminal
143
and an enable out bar signal ({overscore (eout)}) at terminal
141
. According to the prior art, the control signals eout and {overscore (eout)}, at terminals
143
and
141
, respectively, were supplied to prior art half-rail differential logic circuit
100
A as control signals ein and {overscore (ein)} as discussed below.
As discussed above, prior art half-rail differential logic circuit
100
A required an enable in (ein) signal, coupled to the gate of NFET
121
and NFET
125
, and an enable in bar signal ({overscore (ein)}), coupled to the gate of NFET
101
. The control signals ein and {overscore (ein)} were supplied by prior art control circuit
100
B from terminals
143
and
141
, respectively. When multiple prior art half-rail differential logic circuits
100
A were cascaded together, prior art control circuit
100
B and control signals ein and {overscore (ein)} were necessitated to ensure that each prior art half-rail differential logic circuit
100
A switched or “fired” only after it had received an input from the previous stage.
Cascading is well known in the art. For a more detailed discussion of the cascading of prior art half-rail differential logic circuits
100
A, and the operation of prior art half-rail differential logic circuit
100
A and prior art control circuit
100
B, the reader is referred to the ISSC97 PAPER 25.6 discussed above. A more detailed discussion of the operation of prior art half-rail differential logic circuit
100
A and prior art control circuit
100
B is omitted here to avoid detracting from the invention.
As noted above, when multiple prior art half-rail differential logic circuits
100
A were cascaded together, each prior art half-rail differential logic circuit
100
A required prior art control circuit
100
B to ensure that each prior art half-rail differential logic circuit
100
A switched or “fired” only after it had received an input from the previous stage. However, prior art control circuit
100
B was extremely complex, requiring at least six additional transistors and several circuit lines. Consequently, prior art half-rail differential logic circuit
100
A required significant addition components and space. This, in turn, meant that prior art half-rail differential logic circuit
100
A required more silicon, a more complex design and more components to potentially fail. In addition, prior art control circuit
100
B not only added complexity to prior art half-rail differential logic circuits
100
A, but it also loaded the output nodes
111
and
113
of prior art half-rail differential logic circuit
100
A and drew current from output nodes
111
and
113
of prior art half-rail differential logic circuit
100
A to charge the control signals ein and {overscore (ein)}. In addition, in the prior art, if prior art control circuit
100
B were made small, the control signals ein and {overscore (ein)} were slow, and this slowed down the operation of prior art half-rail differential logic circuit
100
A. Consequently, there was pressure to increase the size of prior art control circuit
100
B. However, Increasing the size of prior art control circuit
100
B to speed up the control signals ein and {overscore (ein)} also increased the loading on the output nodes
111
and
113
of prior art half-rail differential logic circuit
100
A and therefore slowed down the evaluation of logic
123
.
What is needed is a method and apparatus for creating half-rail differential logic that does not require the complex control circuitry of prior art half-rail differential logic circuits and is therefore simpler, more space efficient and is more reliable than prior art half-rail differential logic circuits.
SUMMARY OF THE INVENTION
According to the invention, the prior art control circuitry is eliminated. The clocked half-rail differential logic circuit of the invention is instead activated from a delayed clock. According to the invention, when clocked half-rail differential logic circuits of the invention are cascaded together, a delayed clock is provided for each clocked half-rail differential logic circuit of the invention. Each delayed clock is timed to at least the delay of the previous clocked half-rail differential logic circuit. Consequently, according to the invention, a delay time is introduced to ensure each clocked half-rail differential logic circuit of the invention is switched or “fired” only after it has received an input from the previous clocked half-rail differential logic circuit.
According to the invention, clocked half-rail differential logic circuits do not require the significant additional components required in the prior art. This, in turn, means that the clocked half-rail differential logic circuits of the invention require less space, are simpler and have fewer components to potentially fail. In addition, clocked half-rail differential logic circuits of the invention eliminate the loading of the output nodes of the half-rail differential logic circuit since there are no control signals ein and {overscore (ein)}, and therefore no prior art control circuits to draw current from the output nodes to charge the control signals ein and {overscore (ein)}. Consequently, using the clocked half-rail differential logic circuits of the invention, speed is increased because there is less loading on the output nodes and the clocked half-rail differential logic circuit of the invention can start evaluating once a differential voltage develops between the complementary inputs coming from the previous clocked half-rail differential logic circuit.
In particular, one embodiment of the invention is a cascaded chain of clocked half-rail differential logic circuits. The chain includes a first clocked half-rail differential logic circuit. The first clocked half-rail differential logic circuit includes: a first clocked half-rail differential logic circuit clock input terminal; at least one first clocked half-rail differential logic circuit data input terminal; and at least one first clocked half-rail differential logic circuit data output terminal.
The cascaded chain also includes a second clocked half-rail differential logic circuit. The second clocked half-rail differential logic circuit includes: a second clocked half-rail differential logic circuit clock input terminal; at least one se

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