Clocked gating based on measured performance

Details Clocked gating based on measured performance Clocked gating based on measured performance

2006-10-31

2006-10-31

Garbowski, Leigh M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07131090

ABSTRACT:
A method of determining a forced gating function for at least one of a plurality of clocked state-holding elements. The forced gating function compares the input and output of said at least one clocked state-holding element. The method simulates the performance of the element for different implementation conditions; measures the performance of the element for each condition, and determines the implementation of the forced gating function using the measured performances.

REFERENCES:
patent: 6434704 (2002-08-01), Dean et al.
patent: 6536024 (2003-03-01), Hathaway
patent: 6643829 (2003-11-01), Borkovic et al.
T. Lang et al., “Individual Flip-Flops with Gated Clocks for Low Power Datapaths,” IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 44, No. 6, Jun. 1997, pp. 507-516.

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