Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2002-08-23
2004-07-20
Le, Don (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S028000, C326S121000
Reexamination Certificate
active
06765415
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to logic circuits and, more particularly, to clocked full-rail differential logic circuits.
BACKGROUND OF THE INVENTION
One example of a prior art full-rail differential logic circuit is presented and discussed at page 112, and shown in FIG.
3
(
c
), in “HIGH SPEED CMOS DESIGN STYLES” by Bernstein et al. of IBM Microelectronics; Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park, Norwell, Mass., 02061; ISBN 0-7923-8220-X, hereinafter referred to as the Bernstein et al. reference, which is incorporated herein by reference, in its entirety, for all purposes.
FIG. 1
shows a prior art full-rail differential logic circuit
100
similar to that discussed in the Bernstein et al. reference. As seen in
FIG. 1
, prior art full-rail differential logic circuit
100
included six transistors: PFET
105
, PFET
107
, NFET
109
, PFET
115
, PFET
117
and NFET
121
. Prior art full-rail differential logic circuit
100
also included: differential logic
123
with inputs
151
and
153
; out terminal
111
; and outBar terminal
113
. Prior art full-rail differential logic circuit
100
is activated from a delayed clock signal CLKA. As shown in
FIG. 1
, signal CLKA was supplied to: gate
116
of PFET
115
; gate
118
of PFET
117
; gate
129
of NFET
109
; and gate
122
of NFET
121
.
Prior art full-rail differential logic circuit
100
worked reasonably well, however, during the evaluation phase, prior art full-rail differential logic circuit
100
drew excess power unnecessarily as the relevant inputs,
151
or
153
, to logic network
123
were transitioning low to shut off the path of one of the complementary output terminals, out terminal
111
or outBar terminal
113
, to ground. The high output terminal, out terminal
111
or outBar terminal
113
, therefore experienced a “dip” during the transition when the inputs
151
or
153
switched from high to low and a short circuit current, or crossbar current, path was established from Vdd
102
to ground. This “dip” was undesirable and resulted in significant power being wasted.
In addition, the structure of prior art full-rail differential logic circuit
100
was particularly susceptible to noise. This problem was extremely undesirable, and damaging, since, typically, multiple prior art full-rail differential logic circuits
100
were cascaded in long chains (not shown) of prior art full-rail differential logic circuits
100
. In these chain configurations, the susceptibility of prior art full-rail differential logic circuit
100
to noise meant that each successive stage of the chain contributed additional noise and was even more adversely affected by the noise than the previous stage. Consequently, a few stages into a chain of prior art full-rail differential logic circuits
100
, noise became the dominant factor in the chain.
What is needed is a full-rail differential logic circuit that does not experience the large “dip” experienced by prior art full-rail differential logic circuit
100
and is therefore more power efficient. In addition, it is desirable to have a full-rail differential logic circuit that is more resistant to noise than prior art full-rail differential logic circuit
100
.
SUMMARY OF THE INVENTION
According to the present invention, clocked full-rail differential logic circuits include shut-off devices to minimize the “dip” at the high output node that was associated with prior art clocked full-rail differential logic circuits. The shut-off device of the invention isolates the high output terminal immediately from the input terminals when the complementary output terminal is pulled to ground. Consequently, according to the present invention, the window period, or path, for the short circuit current, or crossbar current, is significantly decreased and power is saved.
In addition, since clocked full-rail differential logic circuits with shut-off include a shut-off device, the high output terminal is isolated from the input terminals and the noise immunity of the clocked full-rail differential logic circuits with shut-off of the invention is significantly better than prior art clocked full-rail differential logic circuits because noise on the input terminal does not affect the high output terminal after evaluation. Consequently, the clocked full-rail differential logic circuits with shut-off of the invention are better suited for application in cascaded chains.
As discussed above, the clocked full-rail differential logic circuits with shut-off of the invention can be cascaded together to form the chains commonly used in the industry. When the clocked full-rail differential logic circuits with shut-off of the invention are cascaded together, the advantages of the clocked full-rail differential logic circuits with shut-off of the invention are particularly evident and the gains in terms of noise immunity, power efficiency, size reduction and flexibility are further pronounced.
In particular, one embodiment of the invention is a cascaded chain of clocked full-rail differential logic circuits with shut-off. The chain includes a first clocked full-rail differential logic circuit with shut-off. The first clocked full-rail differential logic circuit with shut-off includes: a first clocked full-rail differential logic circuit with shut-off clock input terminal; at least one first clocked full-rail differential logic circuit with shut-off data input terminal; and at least one first clocked full-rail differential logic circuit with shut-off data output terminal.
The cascaded chain also includes a second clocked full-rail differential logic circuit with shut-off. The second clocked full-rail differential logic circuit with shut-off includes: a second clocked full-rail differential logic circuit with shut-off clock input terminal; at least one second clocked full-rail differential logic circuit with shut-off data input terminal; and at least one second clocked full-rail differential logic circuit with shut-off data output terminal.
According to the invention, the at least one first clocked full-rail differential logic circuit with shut-off data output terminal is coupled to the at least one second clocked full-rail differential logic circuit with shut-off data input terminal to form the chain. According to the invention, a first clock signal is coupled to the first clocked full-rail differential logic circuit with shut-off clock input terminal and a second clock signal is coupled to the second clocked full-rail differential logic circuit with shut-off clock input terminal. According to the invention, the second clock signal is delayed with respect to the first clock signal by a predetermined delay time.
In one embodiment of the invention, a delay circuit is coupled between the first clocked full-rail differential logic circuit with shut-off clock input terminal and the second clocked full-rail differential logic circuit with shut-off clock input terminal to provide the predetermined delay time.
One embodiment of the invention is a clocked full-rail differential logic circuit with shut-off that includes a clocked full-rail differential logic circuit with shut-off out terminal and a clocked full-rail differential logic circuit with shut-off outBar terminal.
In one embodiment of the invention, the clocked full-rail differential logic circuit with shut-off also includes a first node, the first node is coupled to a first supply voltage.
In one embodiment of the invention, the clocked full-rail differential logic circuit with shut-off also includes a first transistor, the first transistor including a first transistor first flow electrode, a first transistor second flow electrode and a first transistor control electrode. The first node is coupled to the first transistor first flow electrode and the first transistor second flow electrode is coupled to the clocked full-rail differential logic circuit with shut-off out terminal. The first transistor can also include a back bias input terminal having a back bias voltage thereon.
In one embodiment of the invention,
Choe Swee Yew
Klass Edgardo F.
Gunnison McKay & Hodgson, L.L.P.
Le Don
McKay Philip J.
Sun Microsystems Inc.
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