Clocked full-rail differential logic with sense amplifiers

Details Clocked full-rail differential logic with sense amplifiers Clocked full-rail differential logic with sense amplifiers

2002-01-29

2003-09-23

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S113000, C326S121000

Reexamination Certificate

active

06624664

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to logic circuits and, more particularly, to full-rail differential logic circuits.
BACKGROUND OF THE INVENTION
One example of a prior art full-rail differential logic circuit is presented and discussed at page 112, and shown in FIG.
3
(
c
), in “HIGH SPEED CMOS DESIGN STYLES” by Bernstein et al. of IBM Microelectronics; Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park, Norwell, Mass., 02061; ISBN 0-7923-8220-X, hereinafter referred to as the Bernstein et al. reference, which is incorporated herein by reference, in its entirety, for all purposes.
FIG. 1
shows a prior art full-rail differential logic circuit
100
similar to that discussed in the Bernstein et al. reference. As seen in
FIG. 1
, prior art full-rail differential logic circuit
100
included six transistors: PFET
105
, PFET
107
, NFET
109
, PFET
115
, PFET
117
and NFET
121
. Prior art full-rail differential logic circuit
100
also included: differential logic
123
with inputs
151
and
153
; out terminal
111
; and outBar terminal
113
. Prior art full-rail differential logic circuit
100
is activated from a delayed clock signal CLKA. As shown in
FIG. 1
, signal CLKA was supplied to: gate
116
of PFET
115
; gate
118
of PFET
117
; gate
129
of NFET
109
; and gate
122
of NFET
121
.
Prior art full-rail differential logic circuit
100
worked reasonably well under conditions of a light load, for instance under conditions where fan out is less than four. However, prior art full-rail differential logic circuit
100
was less useful under conditions of a heavy load, for instance, in cases where fan out exceeded four. The shortcomings of prior art full-rail differential logic circuit
100
arose primarily because under heavy load conditions logic network
123
had to be increased in size to act as a driver for the next stage in the cascade. This in turn meant that logic network
123
was large, slow and inefficient. The problem was further aggravated as additional prior art full-rail differential logic circuits
100
were cascaded together to form the chains commonly used in the industry. Consequently, the full potential of prior art full-rail differential logic circuits
100
was not realized and their use was narrowly limited to light load applications.
What is needed is a method and apparatus for creating full-rail differential logic circuits that are capable of efficient use under heavy loads and are therefore more flexible, more space efficient and more reliable than prior art full-rail differential logic circuits.
SUMMARY OF THE INVENTION
The modified full-rail differential logic circuits of the invention include a sense amplifier circuit that is triggered by the delayed clock of the following stage, i.e., the clock input to the sense amplifier circuit of the modified full-rail differential logic circuits of the invention is additionally delayed with respect to the delayed clock that drives the full-rail differential logic. The addition of the sense amplifier circuit, and second delayed clock signal, according to the invention, allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the logic network to provide the driver function. Consequently, the modified full-rail differential logic circuits of the invention are capable of operating efficiently under heavy load conditions without the increased size and the significant reduction in speed associated with prior art full-rail differential logic circuits. In addition, the modified full-rail differential logic circuits of the invention require less space, are simpler, dissipate less heat and have fewer components to potentially fail.
The modified full-rail differential logic circuits of the invention can be cascaded together to form the chains commonly used in the industry. When the modified full-rail differential logic circuits of the invention are cascaded together, the advantages of the modified full-rail differential logic circuits of the invention are particularly evident and the gains in terms of efficiency, size reduction and flexibility are further pronounced.
In particular, one embodiment of the invention is a cascaded chain of modified full-rail differential logic circuits. The chain includes a first modified full-rail differential logic circuit. The first modified full-rail differential logic circuit includes: a first modified full-rail differential logic circuit first clock input terminal; at least one first modified full-rail differential logic circuit data input terminal; at least one first modified full-rail differential logic circuit data output terminal; and a first modified full-rail differential logic circuit second clock input terminal.
The cascaded chain of the invention also includes a second modified full-rail differential logic circuit. The second modified full-rail differential logic circuit includes: a second modified full-rail differential logic circuit first clock input terminal; at least one second modified full-rail differential logic circuit data input terminal; at least one second modified full-rail differential logic circuit data output terminal; and a second modified full-rail differential logic circuit second clock input terminal.
According to the invention, the at least one first modified full-rail differential logic circuit data output terminal is coupled to the at least one second modified full-rail differential logic circuit data input terminal to form the chain. According to the invention, a first clock signal is coupled to the first modified full-rail differential logic circuit first clock input terminal and a second clock signal is coupled to the first modified full-rail differential logic circuit second clock input terminal and the second modified full-rail differential logic circuit first clock input terminal. According to the invention, the second clock signal is delayed with respect to the first clock signal by a predetermined delay time.
In one embodiment of the invention, a delay circuit is coupled between the first modified full-rail differential logic circuit clock input terminal and the second modified full-rail differential logic circuit first clock input terminal to provide the predetermined delay time. In one embodiment of the invention, the delay circuit is also coupled between the first modified full-rail differential logic circuit clock input terminal and the first modified full-rail differential logic circuit second clock input terminal to provide the predetermined delay time.
One embodiment of the invention is a modified full-rail differential logic circuit that includes a modified full-rail differential logic circuit out terminal and a modified full-rail differential logic circuit outBar terminal.
In one embodiment of the invention, the modified full-rail differential logic circuit also includes a first node, the first node is coupled to a first supply voltage.
In one embodiment of the invention, the modified full-rail differential logic circuit also includes a first transistor, the first transistor including a first transistor first flow electrode, a first transistor second flow electrode and a first transistor control electrode. The first node is coupled to the first transistor first flow electrode and the first transistor second flow electrode is coupled to the modified full-rail differential logic circuit out terminal. The first transistor can also include a back bias input terminal having a back bias voltage thereon.
In one embodiment of the invention, the modified full-rail differential logic circuit also includes a second transistor, the second transistor including a second transistor first flow electrode, a second transistor second flow electrode and a second transistor control electrode. The first node is coupled to the second transistor first flow electrode and the second transistor second flow electrode is coupled to the modified full-rail differential logic circuit outBar terminal.
In one embodiment of the invention, the modified full-rail di

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