Clocked full-rail differential logic with sense amplifier...

Details Clocked full-rail differential logic with sense amplifier... Clocked full-rail differential logic with sense amplifier...

2002-12-24

2004-06-15

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S098000, C326S121000, C365S205000

Reexamination Certificate

active

06750679

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to logic circuits and, more particularly, to full-rail differential logic circuits.
BACKGROUND OF THE INVENTION
One example of a prior art full-rail differential logic circuit is presented and discussed at page 112, and shown in FIG.
3
(
c
), in “HIGH SPEED CMOS DESIGN STYLES” by Bernstein et al. of IBM Microelectronics; Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park, Norwell, Mass., 02061; ISBN 0-7923-8220-X, hereinafter referred to as the Bernstein et al. reference, which is incorporated herein by reference, in its entirety, for all purposes.
FIG. 1
shows a prior art full-rail differential logic circuit
100
similar to that discussed in the Bernstein et al. reference. As seen in
FIG. 1A
, prior art full-rail differential logic circuit
100
included six transistors: PFET
105
, PFET
107
, PFET
109
, PFET
115
, PFET
117
and NFET
121
. Prior art full-rail differential logic circuit
100
also included: OUT terminal
111
coupled to a terminal
178
of a base logic portion
123
A of a logic block
123
and OUTBAR terminal
113
coupled to a terminal
179
of a complementary logic portion
123
B of logic block
123
. Prior art full-rail differential logic circuit
100
is activated from a delayed clock signal CLKA. As shown in
FIG. 1A
, signal CLKA was supplied to: gate
116
of PFET
115
; gate
118
of PFET
117
; gate
129
of PFET
109
; and gate
122
of NFET
121
.
Prior art full-rail differential logic circuit
100
worked reasonably well under conditions of a light load, for instance under conditions where fan out is less than four. However, prior art full-rail differential logic circuit
100
was less useful under conditions of a heavy load, for instance, in cases where fan out exceeded four. The shortcomings of prior art full-rail differential logic circuit
100
arose primarily because under heavy load conditions logic network
123
had to be increased in size to act as a driver for the next stage in the cascade. This in turn meant that logic network
123
was large, slow and inefficient. The problem was further aggravated as additional prior art full-rail differential logic circuits
100
were cascaded together to form the chains commonly used in the industry. Consequently, the full potential of prior art full-rail differential logic circuits
100
was not realized and their use was narrowly limited to light load applications.
In addition, as noted above, since prior art full-rail differential logic circuit
100
was a dual rail logic circuit, requiring an output OUT
111
and a complementary output OUTBAR
113
, in the prior art, logic block
123
had to include both a base logic function, via base logic portion
123
A of logic block
123
, such as an AND gate, OR gate, XOR gate, etc. and the complementary logic function, via complementary logic portion
123
B of logic block
123
, such as a NAND gate, NOR gate, XNOR gate, etc.
FIG. 1B
shows one particular embodiment of a prior art full-rail differential logic circuit
100
A that includes a base logic portion
123
A that is an AND gate and a complementary logic port-ion
123
B that is a NAND gate. As shown in
FIG. 1B
, AND gate
123
A includes NFET
161
and NFET
163
connected in series. Input
151
is coupled to the control electrode, or gate, of NFET
161
and input
153
is coupled to the control electrode or gate of NFET
163
. As also shown in
FIG. 1B
, NAND gate
123
A includes NFET
171
and NFET
173
connected in parallel. Input
151
BAR is coupled to the control electrode, or gate, of NFET
171
and input
153
BAR is coupled to the control electrode or gate of NFET
173
. Consequently, in the prior art, four transistors were required to provide the output OUT
111
and its complementary output OUTBAR
113
.
This need in the prior art to include both a base logic function and its complementary logic function resulted in an increase in power usage, an increase in space used, an increase in design complexity, and an increase in heat production.
What is needed is a method and apparatus for creating full-rail differential logic circuits that are capable of efficient use under heavy loads and are more flexible, more space efficient and more reliable than prior art full-rail differential logic circuits.
SUMMARY OF THE INVENTION
The clocked full-rail differential logic circuits with sense amplifier and single-rail logic of the invention include a sense amplifier circuit that is triggered by the delayed clock of the following stage, i.e., the clock input to the sense amplifier circuit of the clocked full-rail differential logic circuits with sense amplifier and single-rail logic of the invention is additionally delayed with respect to the delayed clock that drives the full-rail differential logic. The addition of the sense amplifier circuit, and second delayed clock signal, according to the invention, allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the logic network to provide the driver function. Consequently, the clocked full-rail differential logic circuits with sense amplifier and single-rail logic of the invention are capable of operating efficiently under heavy load conditions without the increased size and the significant reduction in speed associated with prior art full-rail differential logic circuits. As a result, the clocked full-rail differential logic circuits with sense amplifier and single-rail logic of the invention require less space, are simpler, dissipate less heat and have fewer components to potentially fail.
In addition, according to the invention, the complementary logic function of the prior art is replaced by a single transistor appropriately sized to provide the complementary output OUTBAR. Consequently, clocked full-rail differential logic circuits with sense amplifier and single-rail logic of the invention use less power and, therefore, generate less heat, require less space, and are simpler in design so that they are more flexible, more space efficient and more reliable than prior art full-rail differential logic circuits.
The clocked full-rail differential logic circuits with sense amplifier and single-rail logic of the invention can be cascaded together to form the chains commonly used in the industry. When the clocked full-rail differential logic circuits with sense amplifier and single-rail logic of the invention are cascaded together, the advantages of the clocked full-rail differential logic circuits with sense amplifier and single-rail logic of the invention are particularly evident and the gains in terms of efficiency, size reduction and flexibility are further pronounced.
In particular, one embodiment of the invention is a cascaded chain of clocked full-rail differential logic circuits with sense amplifier and single-rail logic of the invention. The chain includes a first clocked full-rail differential logic circuit with sense amplifier and single-rail logic. The first clocked full-rail differential logic circuit with sense amplifier and single-rail logic includes: a first clocked full-rail differential logic circuit with sense amplifier and single-rail logic first clock input terminal; at least one first clocked full-rail differential logic circuit with sense amplifier and single-rail logic data input terminal; at least one first clocked full-rail differential logic circuit with sense amplifier and single-rail logic data output terminal; and a first clocked full-rail differential logic circuit with sense amplifier and single-rail logic second clock input terminal.
The cascaded chain of the invention also includes a second clocked full-rail differential logic circuit with sense amplifier and single-rail logic. The second clocked full-rail differential logic circuit with sense amplifier and single-rail logic includes: a second clocked full-rail differential logic circuit with sense amplifier and single-rail logic first clock input terminal; at least one second clocked full-rail differential logic circuit with sense amplif

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