Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2002-08-23
2004-03-09
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S098000, C326S121000, C326S096000, C327S056000, C327S057000, C365S205000, C365S207000
Reexamination Certificate
active
06703867
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to logic circuits and, more particularly, to full-rail differential logic circuits.
BACKGROUND OF THE INVENTION
One example of a prior art full-rail differential logic circuit is presented and discussed at page 112, and shown in FIG.
3
(
c
), in “HIGH SPEED CMOS DESIGN STYLES” by Bernstein et al. of IBM Microelectronics; Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park, Norwell, Mass., 02061; ISBN 0-7923-8220-X, hereinafter referred to as the Bernstein et al. reference, which is incorporated herein by reference, in its entirety, for all purposes.
FIG. 1
shows a prior art full-rail differential logic circuit
100
similar to that discussed in the Bernstein et al. reference. As seen in
FIG. 1
, prior art full-rail differential logic circuit
100
included six transistors: PFET
105
, PFET
107
, NFET
109
, PFET
115
, PFET
117
and NFET
121
. Prior art full-rail differential logic circuit
100
also included: differential logic
123
with inputs
151
and
153
; out terminal
111
; and outBar terminal
113
. Prior art full-rail differential logic circuit
100
was activated from a clock signal CLKA. As shown in
FIG. 1
, signal CLKA was supplied to: gate
116
of PFET
115
; gate
118
of PFET
117
; gate
129
of NFET
109
; and gate
122
of NFET
121
.
Prior art full-rail differential logic circuit
100
worked reasonably well under conditions of a light load, for instance under conditions where fan out is less than four. However, prior art full-rail differential logic circuit
100
was less useful under conditions of a heavy load, for instance, in cases where fan out exceeded four. The shortcomings of prior art full-rail differential logic circuit
100
arose primarily because under heavy load conditions logic network
123
had to be increased in size to act as a driver for the next stage in the cascade. This in turn meant that logic network
123
was large, slow and inefficient. The problem was further aggravated as additional prior art full-rail differential logic circuits
100
were cascaded together to form the chains commonly used in the industry. Consequently, the full potential of prior art full-rail differential logic circuits
100
was not realized and their use was narrowly limited to light load applications.
In addition during the evaluation phase, prior art full-rail differential logic circuit
100
drew excess power unnecessarily as the relevant inputs,
151
or
153
, to logic network
123
were transitioning low to shut off the path of one of the complementary output terminals, out terminal
111
or outBar terminal
113
, to ground. The high output terminal, out terminal
111
or outBar terminal
113
, therefore experienced a “dip” during the transition when the inputs
151
or
153
switched from high to low and a short circuit current, or crossbar current, path was established from Vdd
102
to ground. This “dip” was undesirable and resulted in significant power being wasted.
In addition, the structure of prior art full-rail differential logic circuit
100
was particularly susceptible to noise. This problem was extremely undesirable, and damaging, since, as discussed above, typically, multiple prior art full-rail differential logic circuits
100
were cascaded in long chains (not shown) of prior art full-rail differential logic circuits
100
. In these chain configurations, the susceptibility of prior art full-rail differential logic circuit
100
to noise meant that each successive stage of the chain contributed additional noise and was even more adversely affected by the noise than the previous stage. Consequently, a few stages into a chain of prior art full-rail differential logic circuits
100
, noise became the dominant factor in the chain.
What is needed is a method and apparatus for creating full-rail differential logic circuits that are capable of efficient use under heavy loads and are therefore more flexible, more space efficient and more reliable than prior art full-rail differential logic circuits. In addition, a full-rail differential logic circuit is needed that does not experience the large “dip” experienced by prior art full-rail differential logic circuit
100
and is therefore more power efficient. Finally, it is desirable to have a full-rail differential logic circuit that is more resistant to noise than prior art full-rail differential logic circuit
100
.
SUMMARY OF THE INVENTION
The clocked full-rail differential logic circuits with sense amplifier and shut-off of the invention include a sense amplifier circuit that is triggered by the delayed clock of the following stage, i.e., the clock input to the sense amplifier circuit of the clocked full-rail differential logic circuits with sense amplifier and shut-off of the invention is additionally delayed with respect to the delayed clock that drives the full-rail differential logic. The addition of the sense amplifier circuit, and second delayed clock signal, according to the invention, allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the logic network to provide the driver function. Consequently, the clocked full-rail differential logic circuits with sense amplifier and shut-off of the invention are capable of operating efficiently under heavy load conditions without the increased size and the significant reduction in speed associated with prior art full-rail differential logic circuits.
In addition, according to the present invention, clocked full-rail differential logic circuits with sense amplifier and shut-off include shut-off devices to minimize the “dip” at the high output node that was associated with prior art clocked full-rail differential logic circuits. The shut-off device of the invention isolates the high output terminal immediately from the input terminals when the complementary output terminal is pulled to ground. Consequently, according to the present invention, the window period, or path, for the short circuit current, or crossbar current, is significantly decreased and power is saved.
In addition, since clocked full-rail differential logic circuits with sense amplifier and shut-off include a shut-off device, the high output terminal is isolated from the input terminals and the noise immunity of the clocked full-rail differential logic circuits with sense amplifier and shut-off of the invention is significantly better than prior art clocked full-rail differential logic circuits because noise on the input terminal does not affect the high output terminal after evaluation. Consequently, the clocked full-rail differential logic circuits with sense amplifier and shut-off of the invention are better suited for application in cascaded chains.
As discussed above, the clocked full-rail differential logic circuits with sense amplifier and shut-off of the invention can be cascaded together to form the chains commonly used in the industry. When the clocked full-rail differential logic circuits with sense amplifier and shut-off of the invention are cascaded together, the advantages of the clocked full-rail differential logic circuits with sense amplifier and shut-off of the invention are particularly evident and the gains in terms of noise immunity, power efficiency, size reduction and flexibility are further pronounced.
In particular, one embodiment of the invention is a cascaded chain of clocked full-rail differential logic circuits with sense amplifier and shut-off. The chain includes a first clocked full-rail differential logic circuit with sense amplifier and shut-off. The first clocked full-rail differential logic circuit with sense amplifier and shut-off includes: a first clocked full-rail differential logic circuit with sense amplifier and shut-off first clock input terminal; at least one first clocked full-rail differential logic circuit with sense amplifier and shut-off data input terminal; at least one first clocked full-rail differential logic circuit with sense amplifier and shut-off data output terminal; and a first clocked f
Choe Swee Yew
Klass Edgardo F.
Gunnison McKay & Hodgson, L.L.P.
McKay Philip J.
Sun Microsystems Inc.
Tan Vibol
LandOfFree
Clocked full-rail differential logic with sense amplifier... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Clocked full-rail differential logic with sense amplifier..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clocked full-rail differential logic with sense amplifier... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3260081