Clocked cycle latch circuit

Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor

Reexamination Certificate

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Details

C326S098000, C326S095000, C327S216000, C327S198000, C327S142000

Reexamination Certificate

active

06970018

ABSTRACT:
A cycle latch includes a control circuit which increases the pull-up rate of a storage node by conditionally discharging the feedback node in a cross-coupled inverter keeper structure. The cycle latch includes an NMOS transistor switch for transferring an input value to the storage node, and two more NMOS transistors connected in series for performing the function of the control circuit. By connecting the storage node to a pre-discharged feedback node and then driving the latch with a low-swing clock, improved performance in terms of delay times, energy consumption, and robustness is achieved.

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James Tschanz et al. Microprocessor Research Labs, Intel Corporation; “Comparative Delay and Energy of Single Edge-Triggered & Dual Edge-Triggered Pulsed Flip-Flops for High-Performance Microprocessors;” pp. 147-152, no date.
FA 8.5: Flow-Through Latch and Edge-Triggered Flip-flop Hybrid Elements; ISSCC96/Session 8:/Digital Clocks and Latches/Paper FA 8.5; 1995 IEEE International Solid State Circuits Conference; Digest of Technical Papers 138-139; Feb. 8, 1996.

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