Clock tree synthesizer for balancing reconvergent and...

Details Clock tree synthesizer for balancing reconvergent and... Clock tree synthesizer for balancing reconvergent and...

2002-06-26

2004-07-13

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06763513

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to computer-aided design (CAD) tools for generating integrated circuit (IC) layouts, and in particular to a clock tree synthesizer for balancing reconvergent and crossover clock trees for IC layouts.
2. Description of Related Art
FIG. 1
is a data flow diagram illustrating a prior art integrated circuit design process. An IC designer initially generates a register transfer language (RTL) netlist
10
describing an IC as a set logic blocks linked though signal paths (“nets”). An RTL netlist
10
often describes the logic blocks somewhat abstractly, using mathematical statements to define the boolean logic they are to carry out. After employing tools
12
to simulate and verify the behavior of the circuit described by RTL level netlist
10
, the designer uses a synthesis tool
14
to convert the RTL level netlist
10
into a “gate level” netlist
16
describing the logic blocks more concretely by referencing the particular circuit devices (cells) that are to interconnect their terminals. A cell library
18
describes each kind of cell gate level netlist
16
may incorporate into the IC, and the gate level netlist does so by referencing their descriptions in cell library
18
.
After employing tools
12
to simulate and verify behavior of the circuit described by gate level netlist
16
, the designer uses a layout tool
20
to generate a layout
22
for the IC design described by gate level netlist
16
. Layout
22
is a data file describing how and where each cell is to be formed in a semiconductor substrate and indicating how the various signal paths (“nets”) interconnecting them are to be formed and routed. Layout tool
20
consults cell library
18
to determine the size, shape and internal layout of each cell. As it designs the nets interconnecting cell terminals, layout tool
20
tries to satisfy various constraints
24
the designer places on cell placement and path routing.
After layout tool
20
generates IC layout
22
, a netlist compiler
26
processes layout
22
to produce another “layout level” netlist
28
modeling the circuit as a set of library cells interconnected by the nets designed by layout tool
20
. Inclusion of behavioral models of the nets renders layout level netlist
28
a more accurate model of the behavior of the IC than RTL and gate level netlists
10
and
16
because the nets affect the speed and other characteristics of the signals passing between cells. The designer may again employ simulation and verification tools
12
to determine whether layout level netlist
28
describes an IC that will behave as expected. The layout process is typically iterative in that layout tool
20
iteratively modifies layout
22
until it arrives at a layout satisfying all constraints
24
.
As a part of the process of generating layout
22
for an IC employing synchronous logic, layout tool
20
employs a clock tree synthesizer (CTS)
30
to develop a clock tree for the IC. A “clock tree” is a network of buffers for delivering one or more clock signals to various cells of the IC such as registers, latches, flip-flops and the like (herein below referred to as “sinks”) that time their operations in response to edges of a clock signal.
FIG. 2
illustrates a portion of a typical synchronous logic circuit
32
including logic stages
34
and
35
having input and output signals linked through a set of sinks
36
-
38
clocked by a clock signal CLK
1
. Since the gates forming logic stages
34
and
35
are unclocked, the signal path delays through logic stages
34
and
35
can vary with the nature the gates forming their internal logic and with IC temperature and process variations. Although the signal path delays through logic stages
34
and
35
can be somewhat unpredictable, sinks
36
-
38
allow state changes in the input signals to logic stages
34
and
35
to occur only on edges of clock signal CLK
1
, and those state changes are highly predictable when the clock signal is derived from a stable source. Thus registers
36
-
38
render the timing of state changes in signals passing from stage-to-stage highly predictable even though the path delays through the stages themselves cannot be predicted with high accuracy.
FIG. 3
is a schematic diagram illustrating a simple clock tree
40
, as might be designed by CTS
30
of
FIG. 1
, for delivering a clock signal CLK
1
entering an IC at an entry point
42
to a set of twelve sinks
44
. (In practice a clock tree may ICs deliver clock signals to thousands of sinks.) Clock tree
40
includes a set of branching signal paths
46
with buffers
48
inserted into various branches to prevent clock signal CLK
1
from attenuating too much as the tree fans the CLK
1
signal out to sinks
44
.
Since sinks
44
are distributed about the semiconductor substrate space occupied by the IC, signal distances and path delays from entry point
42
to sinks
44
can vary significantly. Therefore, as illustrated in
FIG. 4
, when it is necessary to ensure that clock signal edges arrive at all sinks
44
at the same time with a high degree of accuracy, CTS
30
of
FIG. 1
“balances” clock tree
40
by inserting additional buffers
48
in selected branches of the tree.
The delay between arrival of an edge of the CLK
1
signal at entry node
42
and subsequent arrival of that edge at any one of sinks
44
is primarily a function of the capacitance of the various branches of tree
40
the CLK
1
signal traverses as it travels from entry node
42
to each sink
44
. The capacitance of a branch is in turn a function of path distance, its proximity to nearby conductors and the dielectric constants of insulating materials therebetween. As the capacitance of the path the CLK
1
signal follows to any sink
44
increases, the rise and fall times of CLK
1
signal edges decrease, thereby increasing the delay with which state changes in the CLK
1
signal appear at the clock inputs of the sync. When CTS
30
alters the clock tree design to insert a buffer
48
into a branch of clock tree
40
, the buffer provides additional current to charge or discharge the capacitance of the segment of the branch it drives, thereby increasing rise and fall times of clock signal edges and decreasing the overall CLK
1
signal path delay to the sinks downstream of the buffer. The number and positions of buffers
48
inserted into a given branch of a clock tree, as well as size (power) and switching speed characteristics of the buffers, affect the amount by which they speed up a clock signal passing though that branch.
To balance a clock tree
40
that it has established, clock CTS
30
of
FIG. 1
first determines path delays within the clock tree in part by analyzing IC layout to determine path signal lengths and capacitances. Clock tree CTS
30
then adds one or more buffers
48
to various branches of the tree as needed to ensure that clock tree
40
delivers the CLK
1
signal to all sinks
44
with a timing variation (“skew”) that is within a specified limit. In doing so, CTS
30
may adjust the position of each buffer
48
within the branch, as well as the size or switching speed characteristics of the buffer, to finely adjust the amount by which the buffer will speed up the CLK
1
signal.
For example to balance tree
40
, CTS
30
estimates the path delay from node
40
A to nodes
40
B and
40
C of FIG.
3
and then, as illustrated in
FIG. 4
, adds one or more buffers
48
to the slower of the two paths sized and positioned to ensure that the CLK
1
signal will arrive concurrently at nodes
40
B and
40
C. CTS
30
compares the estimated path delays in the branches extending from nodes
40
A and
40
B to nodes
40
D-
40
H, determines which the branch (
40
C to
40
H), has the shortest delay, and then adds buffers
48
to all other branches to set their delays as close as possible to that short delay. A similar balancing algorithm can be used to balance very large clock trees.
Initially CTS
30
only roughly specifies the routing of the various branches
46
of clock tree

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