Clock tree synthesis for low power consumption and low clock...

Details Clock tree synthesis for low power consumption and low clock... Clock tree synthesis for low power consumption and low clock...

2007-05-08

2007-05-08

Lin, Sun James (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

10935670

ABSTRACT:
A method for low power clock tree synthesis using buffer insertion, removal and resizing for high-speed VLSI design is proposed. A developed tool can be embedded in the existing clock tree synthesis design flow to ensure satisfying both specifying database constrains and clock skew constrains. For a given clock tree netlist, location information of buffers, parameters of wires and buffers' timing and power library are all included. Buffer delay and wire delay of the given clock tree netlist are calculated first. Then, a feasible solution is solved if an input netlist is not feasible for given constrains. Finally, a modified low power clock tree netlist, which satisfies timing specifications, is obtained using the proposed method.

REFERENCES:
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Mehta, A.D., Chen. Y.P., Menezes, N., Wong, D.F. and Pileggi, L.T., “Cluster and Load Balancing for Buffered Clock Tree Synthesis”, Department of Computer Sciences, The University of Texas at Austin, © 1997, pp. 217-223.
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Neves, J.L. and Friedman, E.G., “Design Methodology for Synthesizing Clock Distribution Networks Exploiting Nonzero Localized Clock Skew”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 4, No. 2, Jun. 1996, pp. 286-291.
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