Clock tree synthesis for a hierarchically partitioned IC layout

Details Clock tree synthesis for a hierarchically partitioned IC layout Clock tree synthesis for a hierarchically partitioned IC layout

2002-01-09

2004-06-15

Whitmore, Stacy A. (Department: 2812)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06751786

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to computer-aided design tools for generating hierarchical integrated circuit (IC) layouts, and in particular to a method for synthesizing a clock tree for a hierarchically partitioned IC layout.
2. Description of Related Art
Hierarchical IC Layouts
A “cell library” is a data base of models of various circuit components (“cells”) an integrated circuit (IC) designer can incorporate into an IC design. The cell library includes behavioral models of each cell and also a physical model of each cell showing placement and routing (P&R) tools how the cell is to be laid out in an a semiconductor substrate when included in an IC.
An IC designer typically creates a “netlist” describing the IC by referencing the library cells forming it and indicating how the terminals of the cells are logically interconnected. After having created the netlist, and having used a circuit simulator and other tools to the verify the behavior of the circuit described by the netlist, an IC designer typically provides the netlist as input to an automated P&R tool which designs the physical layout of the IC on a semiconductor substrate. The P&R tool consults the cell library to determine how to lay out each cell described by the netlist and then determines where to place each cell in the substrate and how to form signal, power and ground paths for connecting the cells to one another.
The netlist that the designer produces usually describes an IC as a hierarchy of modules. For example as illustrated in
FIG. 1
, the netlist may consider an entire IC design to be a single top level (level 1) module M
0
. A set of three level 2 modules M
1
-M
3
and some individual cells
10
not included in any of modules M
1
-M
3
form module M
0
. Each module M
1
-M
3
may in turn be formed by level 3 modules or cells. In the example of
FIG. 1
, module M
2
includes a set of four level 3 modules M
4
-M
7
and some individual cells
11
not included in any of modules M
4
-M
7
. Modules M
4
-M
7
reside at the lowest level (level 3) of the modular hierarchy because they are formed only by base level cells
12
which are not organized into submodules. Although
FIG. 1
illustrates a circuit design having only a few modules organized into a three hierarchical levels, a large IC design may include hundreds or thousands of modules organized into many more hierarchical levels.
An IC designer organizes a IC design as a hierarchy of modules to make it easier to conceptualize the IC. However since a typical P&R tool is interested only in finding a suitable position for each cell of the design, it ignores the modularity of the design and places each cell wherever it is convenient to do so and does not try to keep all of the cells of a given module within a separately identifiable area of a semiconductor substrate. Hence the cells forming various modules of a hierarchical design usually end up being intermingled to some extent in an IC layout.
Partitioned Layouts
A designer may want to produce a “partitioned” IC layout in which one or more selected modules are to be placed in separate partitions of a substrate. For example
FIG. 2
illustrates a floor plan for a semiconductor substrate
16
upon which the IC of
FIG. 1
may be formed.
FIG. 1
illustrates how the IC layout of
FIG. 1
might be partitioned. In this example, module M
1
is placed within partition P
1
, modules M
5
and M
7
are placed within partition P
2
, modules M
4
and M
6
are placed in partitions P
3
and P
4
, respectively. All modules and cells not included in any “base level” partition P
1
-P
4
(in this example only module M
3
and cells
10
and
11
of modules M
0
and M
2
_) may be placed anywhere within a “top level” partition P
0
. For simplicity partitions P
0
-P
4
are illustrated as being rectangular, but partitions may be of more complicated shapes. Given a pin assignment plan indicating the places along the boundaries of the various partition where signal paths are to cross between partitions, P&R tools can independently lay out each partition, provided that they are able to keep the layouts within the partition boundaries specified by the floor plan.
It can be advantageous to partition a design because a P&R tool can often separately layout several partitions of a design faster than it can lay out an unpartitioned design. Also when a designer places a selected module of a design in an identifiable area of a substrate so that its cells are not intermingled with cells of other modules, the designer may be able to later modify that particular module without greatly affecting the layout of other modules. However, as discussed below, problems associated with clock tree synthesis tend to increase the interdependence of partition layouts, thereby complicating the layout process after one partition is changed.
Clock Tree Synthesis
Digital ICs typically implement synchronous logic circuits that are clocked by externally generated clock signals. For example
FIG. 3
shows a simple example of a synchronous logic circuit within an IC
30
. A latch
30
latches two IC input signals A and B onto inputs of a logic circuit
34
and an IC input signal C onto an input of a logic circuit
36
. Logic circuit
34
carries out logic operations on signals A and B to produce an output signal D latched onto another input of logic circuit
36
by a latch
38
. Logic circuit
36
processes signals C and D to form a signal E, and a latch
39
latches signal E onto an output terminal of IC
30
. A CLOCK signal supplied as input to IC
30
clocks all of latches
30
,
38
and
39
. For the circuit to operate synchronously, it is necessary to route the CLOCK signal to each latch
36
,
38
and
39
in such a way that edges of the CLOCK signal arrive substantially at the same time at all latches.
While
FIG. 3
shows only three devices being clocked by the CLOCK signal, a typical IC can have hundreds or thousands of clocked devices (“syncs”) such as latches, registers and flip-flops. After a P&R tool has generated an IC layout in which all of the cells (including all of the syncs) have been placed and routed, a “clock tree synthesis” tool designs a clock tree for routing CLOCK edges from the IC's clock input terminal concurrently to all syncs.
FIG. 4
is a schematic diagram illustrating a clock tree
40
for delivering a CLOCK signal from an IC input pin
42
to several syncs
44
.
FIG. 5
illustrates positions of syncs
44
within an IC substrate
46
after a P&R tool has generated a full-chip IC layout. A typical clock tree synthesis tool begins designing the clock tree of
FIG. 4
by assigning each sync
44
into one of a set of “clusters”
48
as illustrated in FIG.
6
. The clock tree will deliver the CLOCK signal to the syncs
44
of each cluster
48
through a separate one of signal buffers
50
(FIG.
4
), and therefore each cluster
48
will include no more than the maximum number of syncs
44
a single buffer
50
can drive. To ensure that CLOCK signal edges travel from the output of each buffer
50
to all syncs
44
it drives with as nearly as possible the same delay, the clock tree synthesis tool groups only nearby syncs
44
into the same cluster
48
. This ensures that the CLOCK signal path distance from each buffer
50
to the syncs it drives will be substantially similar regardless of where the buffer is placed.
Having grouped all syncs
44
into clusters and having specified an approximate location for each buffer
50
near the cluster it drives, the synthesis tool next groups nearby buffers
50
into clusters. As illustrated in
FIG. 4
, the CTS tool has grouped twelve buffers
50
into four clusters
52
. The CTS tool then provides a separate buffer
54
to drive each cluster
52
of buffers
50
. After specifying an approximate location for each second level buffer
54
near the cluster of first level buffers
50
it is to drive, the CTS tool groups buffers
54
into clusters
56
, each driven by a separate buffer
58
. All buffers
58
are then grouped into a sin

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