Clock tree network in a field programmable gate array

Details Clock tree network in a field programmable gate array Clock tree network in a field programmable gate array

2008-05-20

2008-05-20

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S040000, C326S047000, C326S101000, C327S141000, C327S144000, C327S150000, C327S156000

Reexamination Certificate

active

11387636

ABSTRACT:
A clock tree distribution network for a field programmable gate array comprises an interface with a root signal chosen from at least one of an external clock signal, an internal clock signal, a plurality of phase lock loop cell output signals and programmable elements. The FPGA includes a logic array with programmable elements coupling the logic array to a programmable routing architecture and the interface. A routed clock network selects a signal from a clock signal from the interface, a local signal from the logic array through the routing architecture, Vcc or ground, and routes the selected signal to the logic array through the clock tree distribution network. A hardwired clock network selects a signal from a clock signal from the interface or a local signal from the routing architecture, and routes the selected signal to a plurality of flip-flops in the logic array through the clock tree distribution network.

REFERENCES:
patent: 6236229 (2001-05-01), Or-Bach
patent: 6426649 (2002-07-01), Fu et al.
patent: 6889331 (2005-05-01), Soerensen et al.

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