Clock tree network in a field programmable gate array

Details Clock tree network in a field programmable gate array Clock tree network in a field programmable gate array

2003-05-28

2004-11-30

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S040000, C326S047000, C326S101000, C327S141000, C327S144000, C327S150000, C327S156000

Reexamination Certificate

active

06825690

ABSTRACT:

BACKGROUND OF THE SYSTEM
1. Field of the System
The present system relates to field programmable gate array (FPGA) devices. More specifically, the system relates to a clock tree network in an FPGA having a central clock tree distribution cluster that is configured to distribute the root signals from the phase locked loop to the logic clusters through routed clock clusters and hardwired clock clusters.
2. Background
FPGAs are known in the art. An FPGA comprises any number of logic modules, an interconnect routing architecture and programmable elements that may be programmed to selectively interconnect the logic modules to one another and to define the functions of the logic modules. An FPGA is an array of uncommitted gates with uncommitted wiring channels. To implement a particular circuit function, the circuit is mapped into an array and the wiring channels' appropriate connections are programmed to implement the necessary wiring connections that form the user circuit.
A field programmable gate array circuit can be programmed to implement virtually any set of functions. Input signals are processed by the programmed circuit to produce the desired set of outputs. Such inputs flow from a user's system, through input buffers and through the circuit, and finally back out the user's system via output buffers. Such buffers may provide any or all of the following input/output (I/O) functions: voltage gain, current gain, level translation, delay, signal isolation or hysteresis.
An FPGA core tile may be employed as a stand alone FPGA, repeated in a rectangular array of core tiles, or included with other devices in a system-on-a-chip (SOC). The core FPGA tile may include an array of logic modules, and input/output modules. An FPGA core tile may also include other components such as read only memory (ROM) modules. Horizontal and vertical routing channels provide interconnections between the various components within an FPGA core tile. Programmable connections are provided by programmable elements between the routing resources.
The programmable elements in an FPGA can be either one-time programmable or re-programmable. Re-programmable elements used in FPGA technologies may comprise transistors or other re-programmable elements as is well known to those of ordinary skill in the art. One-time programmable elements used in FPGA technologies may comprise antifuse devices.
As FPGAs grow in size, on-chip clock distribution becomes increasingly important. Clock skew and clock delay impact FPGA performance and the task of managing clock skew and clock delay with conventional clock trees becomes more difficult in large FPGAs. As such, in large, fast FPGAs, the performance limiting element is often clock delay due to large clock networks. Phase locked loops (PLLs) are used to reduce the clock delays inherent in large FPGAs and, thereby improve performance.
There is a need in the art for a clock network that has the ability to interject an internal signal into the root of the distribution tree, at the center of any tile or per tile row or tile column of logic clusters. There is also a need for a clock network that has the ability to shut off power on unused portions of the clock tree. In addition, there is a need for a clock network that has the ability to balance skew among all points within the clock network.
SUMMARY OF THE SYSTEM
A clock tree distribution network for a field programmable gate array comprises an interface that has a root signal chosen from at least one of an external clock signal, an internal clock signal, a plurality of phase lock loop cell output signals and programmable elements. The FPGA includes a logic array that has programmable elements coupling the logic array to a programmable routing architecture and the interface.
A routed clock network selects a signal from between a clock signal from the interface, a local signal from the logic array through the routing architecture, Vcc or ground, and routes the selected signal to the logic array through the clock tree distribution network. A hardwired clock network that selects a signal from between a clock signal from the interface and a local signal from the routing architecture, and routes the selected signal to a plurality of flip-flops in the logic array through the clock tree distribution network.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description of the invention and accompanying drawings which set forth an illustrative embodiment in which the principles of the invention are utilized.


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