Clock tree layout method for semiconductor integrated circuit

Details Clock tree layout method for semiconductor integrated circuit Clock tree layout method for semiconductor integrated circuit

2005-10-05

2008-08-05

Kik, Phallaka (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07409657

ABSTRACT:
By executing the steps of sequentially retrieving buffers on a clock tree from a clock source to input pins of the cells other than the buffers and recognizing the buffer retrieved, organizing a group of the buffers recognized on the clock tree into an instance as a hierarchical block and extracting the hierarchical block as a net list, the part constituting the buffers on the clock tree once designed is organized in the hierarchical block and the hierarchical block are saved as the net list as well as the physical arrangement information of an individual buffer. After the circuit modification or net list change have been made, the hierarchical block previously saved is inserted into the net list, and the hierarchical levels are developed after automated arrangement to reproduce the physic arrangement information of the clock tree.

REFERENCES:
patent: 6053950 (2000-04-01), Shinagawa
patent: 6550045 (2003-04-01), Lu et al.
patent: 2003/0005345 (2003-01-01), Fletcher et al.
patent: 2004/0210857 (2004-10-01), Srinivasan
patent: 3112843 (1998-04-01), None
patent: 2001-308186 (2001-11-01), None
patent: 2003-316843 (2003-11-01), None

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