Clock tree distribution generation by determining allowed...

Details Clock tree distribution generation by determining allowed... Clock tree distribution generation by determining allowed...

2007-05-29

2007-05-29

Lin, Sun James (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

10905970

ABSTRACT:
A method, system and program product are described for generating a clock distribution network on an integrated circuit by determining an allowable placement region for each of a set of clock tree leaf elements in the integrated circuit. This allowable placement region is generated by determining and intersecting a set of sub-regions under different constraints, each of which identifies an area in which the clock tree leaf element is placed to satisfy the respective constraint. Constraints for which sub-regions are determined include timing constraints in the form of slacks and congestion constraints. After allowable placement regions have been determined, the clock tree leaf elements are clustered, and each clock tree leaf element is placed at a location within its allowable placement region which minimizes some cost function for that clustering.

REFERENCES:
patent: 5963728 (1999-10-01), Hathaway et al.
patent: 6182271 (2001-01-01), Yahagi
patent: 6205571 (2001-03-01), Camporese et al.
patent: 6536024 (2003-03-01), Hathaway
patent: 6651224 (2003-11-01), Sano et al.
patent: 2003/0182649 (2003-09-01), Harn

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