Clock tree circuit and semiconductor memory device using the...

Details Clock tree circuit and semiconductor memory device using the... Clock tree circuit and semiconductor memory device using the...

2011-01-11

2011-01-11

Lee, Thomas (Department: 2116)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Correction for skew, phase, or rate

C713S500000, C327S175000

Reexamination Certificate

active

07870414

ABSTRACT:
A semiconductor memory device, which includes a clock tree circuit for correcting the duty cycle of a clock. The device sets a beta ratio to cause a constant duty cycle by using a reference clock having a constant duty cycle in a test mode, and then applies the set beta ratio to a DLL clock outputted from a delay-locked loop. Then, when the duty cycle of the DLL clock, to which the beta ratio has been applied, is not constant, the duty cycle of the DLL clock is corrected in the delay-locked loop.

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