Clock tree adjustable buffer

Details Clock tree adjustable buffer Clock tree adjustable buffer

2005-08-04

2009-08-04

Levin, Naum B (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C327S158000, C327S276000

Reexamination Certificate

active

07571406

ABSTRACT:
An adjustable buffer including a first series of P-channel devices having current electrodes coupled in series between a first voltage supply and a first output node, and a first series of N-channel devices having current electrodes coupled in series between the first output node and a second voltage supply. The control electrodes of the P- and N-channel devices are coupled to a selected one of an input node and a corresponding voltage supply collectively forming first and second sets of selectable connections. The first and second sets of selectable connections are made to adjust delay from the input node to the first output node. A clock distribution system including multiple uniform adjustable buffers coupled between at least one root node and multiple destination nodes, where each uniform adjustable buffer is adjustable between a minimum delay and a maximum delay.

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Yusuke Nitta and Toshihiro Hattori, Clock Distribution Techniques for a 200-MHz RISC Processor, Advanced Microcomputer Development Dept., Semiconductor Technology Development Center, Hirachi, Ltd, Aug. 23, 1999 (Session 6, presentation #3, 1:30-3:10pm).

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