Clock template for configuring a programmable gate array

Details Clock template for configuring a programmable gate array Clock template for configuring a programmable gate array

2001-04-26

2004-05-04

Thompson, A. M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06732347

ABSTRACT:

FIELD OF THE INVENTION
The present invention is directed to the configuration of programmable gate arrays, in general, and more particularly, to a clock template and method of configuring a programmable gate array with a plurality of circuit designs having different clock configurations using the clock template.
BACKGROUND OF THE INVENTION
In the past, field programmable gate array (FPGA) architectures accommodated only configuration of the entire array. Accordingly, with each change in a design and/or the addition of a design, a whole new bit stream had to be generated for configuring or programming the whole FPGA. Recently, however, new FPGA architectures were developed, like the Virtex® series manufactured by Xilinx®, for example, that accommodated a partial reconfiguration even down to an information frame level. For a more detailed understanding of configuration and partial configuration of FPGAs reference is made to two Xilinx® application notes—(1) “Virtex Series Configuration Architecture User Guide”, XAPP151 (v1.5), Sep. 27, 2000, and (2) “Status and Control Semaphore Registers Using Partial Reconfiguration”, by Nick Camilleri, XAPP153 (v1.0), Jun. 7, 1999 which are incorporated by reference herein in their entirety.
With the new architectures, bit streams may be generated piecemeal for configuring portions of an FPGA with a plurality of different designs. But, obstacles remain in connection with fully implementing partial reconfiguration for all cases. Currently, only simple designs may take advantage of partial reconfiguration, like, for example, a design that has the same clock configuration and look up table (LUT)/flip flop (FF) usage as the designs already configured within the FPGA or a design that does not use clocks. Accordingly, one obstacle to overcome is how to handle the partial reconfiguration of designs with different clock configurations.
In the Xilinx® series of Virtex FPGAs, the clock configuration which controls the clock settings and routing throughout a design is embedded within each design. More specifically,
FIG. 1
illustrates the programming structure of the architecture of an FPGA, like the Virtex series, for example. In this architecture example, the FPGA includes a plurality of columns, with each column divided into a number of frames. Each frame is essentially 1bit wide by N bits long and extends the full length of a column. A “shadow register” within each column having the same capacity as a frame of the column accepts data loaded into the FPGA destined for one of the frames of the particular column and temporarily buffers the data until it may load it into the designated frame without interrupting substantially operation of the FPGA. In
FIG. 1
, each column area is distinct and separate from the other column areas. For example, input/output block (IOB) frames of a column are programmed to control input/output routing and configuration, but do not involve configuration logic block (CLB) frames or block random access memory (BRAM) frames. Likewise, BRAM frames are programmed with data and routing configuration that do not involve CLB and IOB frames.
The CLB frames contain programmed design information within that particular column of an M×N FPGA, where M and N are the number of rows and columns of CLBs within the FPGA, respectively. On the other hand, the general clocking or GCLK frames of the center column of the FPGA contain clocking configurations or tree data for all of the programmed designs of the FPGA. With the current architecture of FPGAs, it is a rather complex and difficult operation to program partially a portion of the GCLK column for a particular design of the CLB frames, i.e., all of the clocking information corresponding to all of the designs must be loaded into the GCLK frames for the FPGA to operate properly. Accordingly, for partial reconfiguration, there is a problem that arises when multiple designs are programmed into an FPGA with different clocking structures as will be explained in greater detail herebelow.
A simple example of an FPGA that is split into two halves which are isolated from each other is shown in FIG.
2
. Referring to
FIG. 2
, the left side columns of the FPGA may be programmed with a design A which may have multiple representations and variants referred to as A
1
, A
2
, . . . , A(N). Similarly, the right side columns of the FPGA may be programmed with a design B which may also have multiple representations and variants referred to as B
1
, B
2
, . . . , B(N). Only one design for A may be loaded into the FPGA at any one time. For example, if a new design variant A
2
is loaded into the FPGA, it over-writes the previous design variant A
1
that was stored in the columns of the left hand side thereof. The same procedure may be performed for the variants of design B in the right hand columns. The FPGA needs to be configured in such a way to permit both designs A and B to operate independent of one another. Note that in this simple example, the center column clocking frames are configured with both of the clocking configurations of the designs A and B. In practice, partially reconfiguring the FPGA in this manner is not easily achievable due primarily to the architecture limitations accommodating programming of the center clocking column as mentioned above.
For example, to initially configure an FPGA, a full bit stream is generated for programming the columns of the left hand side and center clocking column with a version of design A and defining the columns of the right hand side as blank or unused as shown in the illustration of FIG.
3
. Notice that the center GCLK clock frames are programmed or configured solely to meet the requirements of the programmed version of design A. Thereafter, the FPGA may be partially reconfigured with a version of design B by programming the right hand columns thereof and the center clocking column which over writes the clocking configuration for the version of design A as shown by the illustration of FIG.
4
. In this configuration, the FPGA can function properly as design B, but can no longer operate as design A because design A's clock configuration was overwritten by the partial reconfiguration of the FPGA with design B. It may be possible to create a bit stream to program design B into the FPGA without programming the center clock column with B's clocking configuration, but then the FPGA will function properly as design A, but not as design B. Accordingly, the same problem exists.
The present invention overcomes the drawbacks described herein above regarding the current architecture of FPGAs and permits partial reconfiguration of an FPGA with multiple designs having different clocking configurations.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, a clock template comprises digital programming information representative of a plurality of different clock configurations corresponding to a plurality of designs for programming clock frames of a programmable gate array (PGA) to configure the PGA in accordance with said corresponding plurality of designs. In one embodiment, the digital information comprises a bit stream for partially reconfiguring the PGA. In another embodiment, the digital information is embedded in digital programming information of at least one of the plurality of designs.
In accordance with another aspect of the present invention, a method of configuring a PGA with a plurality of different designs having different clocking configurations comprises the steps of: creating a high level descriptive design language representation of each of the plurality of designs, each said design representation including a clocking configuration portion; copying said clocking configuration portions from said design representations into a high level descriptive design language clock template; and using said clock template to configure the PGA.
In accordance with yet another aspect of the present invention, a method of configuring a PGA with a plurality of different designs having different clocking configurations comprise

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