Clock synchronous type DRAM with data latch

Details Clock synchronous type DRAM with data latch Clock synchronous type DRAM with data latch

1996-11-25

1997-08-19

Nelms, David C.

Static information storage and retrieval

Read/write circuit

365219, 365220, 365221, G11C 700

Patent

active

056595077

ABSTRACT:
A semiconductor memory device includes a memory cell array, row decoder, bit line pairs, sense amplifier, sense amplifier control circuit, data latch, transfer gate, transfer gate control circuit, and write circuit. The memory cell array has dynamic memory cells arranged in an array form. The row decoder decodes a row address signal to select a desired one of rows of the memory cell array. Each of the bit line pairs is connected to those of the memory cells which are arranged on a corresponding one of columns of the memory cell array. The sense amplifier amplifies data read out on the paired bit lines and positively feeding data back to the paired bit lines to hold the data. The sense amplifier control circuit controls the operation of the sense amplifier. The data latch latches readout data and write data. The transfer gate transfers data between the data latch and the sense amplifier. The transfer gate control circuit controls the transfer gate. The write circuit writes data into the data latch in synchronism with a clock signal. At the time of writing data into the memory cells, data is previously supplied to the data latch by the write circuit and latched in the data latch, and after the transfer gate control circuit controls the transfer gate to supply data to the bit line pairs from the data latch, the sense amplifier control circuit activates the sense amplifier.

REFERENCES:
patent: 4807189 (1989-02-01), Pinkham et al.
patent: 5327386 (1994-07-01), Fudeyasu
patent: 5361236 (1994-11-01), Iwakiri
patent: 5367486 (1994-11-01), Mori et al.
IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991, pp. 479-482, N. Kushiyama et al., "A 12-MHz Data Cycle 4-Mb DRAM with Pipeline Operation".
IEICE Trans. Electron, vol. E77-C, No. 8, Aug. 1994, pp. 1303-1315, S. Ohshima et al., "High Speed DRAMs with Innovative Architectures".

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