Static information storage and retrieval – Read/write circuit
Reexamination Certificate
2002-06-18
2004-01-20
Nguyen, Van Thu (Department: 2824)
Static information storage and retrieval
Read/write circuit
C365S193000, C365S194000, C365S233100, C711S167000, C713S500000
Reexamination Certificate
active
06680866
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly, to a clock synchronous semiconductor memory device for taking in data and a signal applied externally in synchronization with a clock signal. More specifically, the present invention relates to a circuit arrangement for adjusting a data take-in timing of the clock synchronous semiconductor memory device.
2. Description of the Background Art
FIG. 25
is a schematic diagram representing an overall configuration of a conventional semiconductor memory device. In
FIG. 25
, a semiconductor memory device
900
includes a memory circuit
902
having a plurality of memory cells, a clock buffer
904
for generating an internal clock signal according to a clock signal CLK applied externally, a main control circuit
906
for taking in an externally applied command CMD in synchronization with the internal clock signal generated from clock buffer
904
and generating a variety of control signals required for an operating mode designated by this command, an input/output circuit
910
for transferring data between memory circuit
902
and an external device, and an input/output control circuit
908
for controlling the data input/output operation of input/output circuit
910
under the control of main control circuit
906
.
Memory circuit
902
includes a plurality of memory cells arranged in a matrix of rows and columns, a memory cell selecting circuit for selecting a row and a column of memory cells according to an address signal ADD under the control of main control circuit
906
, and a write/read circuit for transferring internal data with input/output circuit
910
. The memory cell selecting circuit and the write/read circuit are activated in a prescribed sequence under the control of main control circuit
906
.
Input/output control circuit
908
controls an external data input operation of input/output circuit
910
according to an externally supplied data strobe signal DQS in a data write operation. In a data output operation, input/output control circuit
908
outputs data strobe signal DQS in synchronization with the data output. Input/output circuit
910
outputs data in synchronization with the internal clock signal in data output operation.
Thus, data strobe signal DQS provides a data take-in timing in the semiconductor memory device in the data write operation, and provides a data take-in timing in an external controller or processor in the data output operation.
Main control circuit
906
decodes an externally supplied command CMD at a rising edge of the internal clock signal generated from clock buffer
904
and generates a variety of control signals necessary for performing the operating mode designated by command CMD. Command CMD includes a plurality of control signals and a specific address signal bit. A command for instructing one operating mode is formed by a combination of logic levels of these signals at the rising edge of clock signal CLK.
FIG. 26
is a schematic diagram representing an arrangement of a data input circuit for one bit of input/output circuit
910
shown in FIG.
25
. In
FIG. 26
, the data input circuit includes a latch circuit
920
for taking in and latching externally supplied data DIN in response to the rise of data strobe signal DQS, a latch circuit
921
for taking in and latching data DIN from outside in response to the fall of data strobe signal DQS, a latch circuit
922
for taking in and latching latch data DILF
0
of latch circuit
920
according to a transfer instructing signal DQSDT, a latch circuit
923
for taking in and latching latch data DILF
1
of latch circuit
921
according to transfer instructing signal DQSDT, a register circuit
924
for taking in and latching latch data DIL
0
of latch circuit
922
in response to a latch transfer instructing signal ZLTTR, and a register circuit
925
for taking in and latching latch data DIL
1
of latch circuit
923
according to latch transfer instructing signal ZLTTR.
Transfer instructing signal DQSDT is generated in the form of a one-shot pulse in response to the fall of data strobe signal DQS.
Latch transfer instructing signal ZLTTR is generated in the form of a one-shot pulse in synchronization with the rise of the internal clock signal in the data write operation. The latch data of register circuits
924
and
925
are transferred in parallel to an internal data bus.
In the internal data bus, an even-numbered data bus corresponding to an even-numbered data address and an odd-numbered data bus corresponding to an odd-numbered data address are provided, and the latch data of register circuits
924
and
925
are transferred to these even-/odd-numbered data buses according to a column address signal.
FIG. 27
is a timing chart representing an operation of the data input circuit shown in FIG.
26
. The operation of the data input circuit shown in
FIG. 26
will be described briefly below with reference to FIG.
27
.
In a data write operation, data strobe signal DQS is input in synchronization with clock signal CLK, and write data DIN is input in synchronization with data strobe signal DQS.
Latch circuit
920
takes in and latches external data DIN in response to the rise of data strobe signal DQS, and generates internal latch data DILF
0
. Latch circuit
921
takes in external data DIN in response to the fall of data strobe signal DQS and generates internal latch data DILF
1
. In the data write operation, transfer instructing signal DQSDT is generated in the form of a one-shot pulse in response to the fall of data strobe signal DQS, and latch circuits
922
and
923
take-in and latch the latch data DILF
0
and DILF
1
of latch circuits
920
and
921
, respectively.
Then, latch transfer instructing signal ZLTTR is generated in the form of a one-shot pulse in response to the rise of clock signal CLK, and register circuits
924
and
925
take in and latch the latch data DIL
0
and DIL
1
of latch circuits
922
and
923
, respectively.
Thus, by internally converting data DIN transferred externally in synchronization with the rising edge and the falling edge of data strobe signals DQS into parallel data, and thereafter, by internally transferring the converted data in parallel according to latch transfer instructing signal ZLTTR in synchronization with clock signal CLK, the valid period width of internal data DIL
0
and DIL
1
can be made equal to one clock cycle period of clock signal CLK, thereby achieving a greater effective valid data width.
Memory circuit
902
operates in synchronization with the internal clock signal, and by performing the above-described processing of the data transferred in synchronization with both the rising edge and the falling edge of data strobe signal DQS, the processing (writing/reading) can be performed with one of the edges of clock signal CLK used as a trigger.
The method of employing data strobe signal DQS to take in the data is called a source synchronous scheme. By transferring the data strobe signal via the same path as the data transfer path, even when the delay time of the data transferred from a controller with respect to the clock signal from a clock generating circuit increases to decrease the valid data width, data can be reliably taken into the semiconductor memory device.
The scheme of transferring data in synchronization with both the rising edge and the falling edge of a clock signal is called the DDR (Double Data Rate) mode. The data transferred serially is taken in, latch transfer instructing signal ZLTTR is generated in synchronization with clock signal CLK internally, and the parallel internal write data is generated in synchronization, for instance, with the rising edge of the internal clock signal. In the memory circuit, the writing and reading process can be performed with a sufficient margin with one of the edges of the clock signal used as a trigger. Thus, data can be transferred at a high speed in synchronization with a high-speed clock signal, the data bandwidth can be increased, and the processing
McDermott & Will & Emery
Nguyen Van Thu
Renesas Technology Corp.
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