Clock-synchronized memory device and the scheduler thereof

Details Clock-synchronized memory device and the scheduler thereof Clock-synchronized memory device and the scheduler thereof

1998-07-16

2000-05-23

Heckler, Thomas M.

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

711105, G06F 104, G06F 1200

Patent

active

060676329

ABSTRACT:
The present invention provides inside a scheduler a shift register, which performs a shift operation in synch with an external clock, or a clock generated thereby. Then, for example, when controlling latency from the supply of a command until the start of a column operation, at the time the command is supplied, a column access signal is stored in a shift register location, which corresponds to its latency. Because the shift register performs a shift operation in synch with a clock, a column access signal is outputted subsequent to a number of clock pulses, which correspond to its latency. A column control circuit, in response to the timing at which this column access signal is outputted, acquires a column address and other data required for a column circuitry operation, and starts a column circuitry operation. A configuration such as this simplifies the operation of the scheduler. In the above-described shift register, setting an internal operation command signal, which starts a prescribed internal operation, makes it possible to readily manage latency up until the start of an arbitrary internal operation.

REFERENCES:
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patent: 5414811 (1995-05-01), Parulski et al.
patent: 5572660 (1996-11-01), Jones
patent: 5729152 (1998-03-01), Leung et al.
patent: 5748551 (1998-05-01), Ryan et al.
patent: 5774739 (1998-06-01), Angle et al.
patent: 5835745 (1998-11-01), Sager et al.

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