Clock synchronized dynamic memory and clock synchronized...

Details Clock synchronized dynamic memory and clock synchronized... Clock synchronized dynamic memory and clock synchronized...

2005-05-24

2005-05-24

Vital, Pierre M. (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S105000, C365S233100

Reexamination Certificate

active

06898683

ABSTRACT:
A synchronous dynamic memory has a clock input buffer receiving an external clock and outputting an input external clock, a command input buffer receiving commands, an address input buffer receiving addresses, and a data input buffer receiving data. During normal operation mode, the clock input buffer supplies the clock to the command, address, and data input buffers. During data hold modes, such as power down mode, the clock input buffer supplies the clock to the command input buffer but not to the address and data input buffers.

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