Clock synchronization semiconductor memory device...

Details Clock synchronization semiconductor memory device... Clock synchronization semiconductor memory device...

2000-03-16

2002-01-08

Mai, Son L. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Serial read/write

C365S219000, C365S230030, C365S239000

Reexamination Certificate

active

06337826

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 11-71606, filed Mar. 17, 1999; and No. 11-335441, filed Nov. 26, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit, and in particular, to a clock synchronization semiconductor integrated circuit for use, for example, in a semiconductor memory such as a clock synchronization DRAM or ROM which has an operation mode for allowing the circuit to internally and continuously serially transfer multi-bit data.
In recent years, the wiring length of semiconductor memories has been increased linearly with the chip size. In addition, the use of finer elements has been contributing to reduction in wiring width and interval. As a result, the wiring resistance and capacity have increased, and the adverse effect of a possible wiring delay on the overall operation speed performance is growing.
Due to its wiring length over which signals are transmitted, a portion of a chip located far away from I/O pads and a control circuit (for example, a peripheral portion of the chip) is more significantly affected by a possible wiring delay than a portion thereof located closer to the input pads and control circuit (for example, a central portion of the chip). As a result, reading data from cell array blocks in the chip peripheral portion requires a larger amount of time than reading data from cell array blocks in the chip central portion.
Some clock synchronization DRAMs have an operation mode or an output data transfer system for loading, in a transfer block, data read out from a plurality of cell array blocks arranged on a chip so that the output data of multiple bits loaded in this transfer block are continuously transferred bit by bit to an output buffer in synchronism with a clock synchronization signal.
The time required to access the plurality of cell array blocks depends on the wiring length of an address signal line between an address buffer and an address decoder for each of the cell array blocks. With conventional on-chip arrangements, accesses to the cell array blocks in the chip peripheral portion require a larger amount of time than accesses to the cell array blocks in the chip central portion.
In the conventional clock synchronization DRAM, however, data read out from the cell array blocks in the chip peripheral portion are loaded in the transfer block simultaneously with data read out from the cell array blocks in the chip central portion.
This is disadvantageous in that only a small timing margin is available in loading, in the transfer block, data read out from the cell array blocks in the chip peripheral portion, which may be caused by an access delay, whereby data transfers from the cell array blocks in the chip peripheral portion may determine the timings for all the cell array blocks. In particular, when data being read out from a cell array block in the chip peripheral portion, which may be subjected to an access delay, the data is to be loaded in the transfer block and if this data has not reached the transfer block yet at the loading timing, then loading of this data may fail.
The above conventional problem will be described below in detail with reference to
FIGS. 1
,
2
, and
3
A-
3
I.
FIG. 1
shows an example of a configuration of part of a conventional clock synchronization DRAM, particularly, of its memory cell arrays and other parts related to output data transfers.
In
FIG. 1
, the memory cell arrays are divided into a plurality of (in this example, four) cell array blocks (each including a sense amplifier)
101
to
104
, and include a row decoder
11
shared by each of the cell array blocks
101
to
104
and column decoders
121
to
124
corresponding to the cell array blocks
101
to
104
, respectively.
An address signal is input to an address buffer
13
, a row address signal is supplied to the row decoder
11
, and a column address signal is supplied to each of the column decoder
121
to
124
.
Data read out from a memory cell in each cell array block
101
to
104
and corresponding to the row and column address signals is stored in a corresponding one of four data line buffers (DQ Buffers)
141
to
144
.
Data DQdata
1
to DQdata
4
stored in the data line buffers
141
to
144
, respectively, are input to a data transfer block
16
through data lines
151
to
154
, respectively, and from the data transfer block
16
, the data are output in a predetermined order in synchronism with a control clock CLK. The data are further output to an output buffer (Dout Buffer)
18
through an output signal line
17
.
In the arrangement of the cell array blocks
101
to
104
, the cell array block
101
is located closer to a chip peripheral portion than the cell array block
104
, and due to the locational relationship between the address buffer
13
and the cell array blocks
101
to
104
, the wiring for each column address signal is relatively long and the lengths of the wirings for column address signals between the address buffer
13
and each of the column decoders
121
to
124
vary.
FIG. 2
shows a conventional example of the data transfer block
16
in FIG.
1
.
The four bit data DQdata
1
to DQdata
4
read out in parallel from the four cell array blocks and stored in the corresponding data line buffers are stored in first to final registers
71
to
74
, respectively, of a shift register in response to the control clock CLK. The data datal to data
4
stored in the first to final registers
71
to
74
are transferred in synchronism with a falling edge of the control clock CLK, and output data Dout data from the final register
74
is output to the output buffer
18
in FIG.
1
.
FIGS. 3A
to
3
I are timing charts showing an example of an operation of the shift register in FIG.
2
.
At a rising edge of the control clock CLK, the data datal in the first stage register
71
is transferred to the second stage register
72
as shift data shiftdatal, the data data
2
in the second register
72
is transferred to the third register
73
as shift data shiftdata
2
, and the data data
3
in the third stage register
73
is transferred to the final stage register
74
as shift data shiftdata
3
. The shift data data
4
in the final stage register
74
changes to the output data Dout data. Likewise, at each rising edge of the sequentially supplied control clock CLK, data is shifted and then transferred. Then, the bit data data
4
, data
3
, data
2
, datal are sequentially output as the output data Dout data.
In this manner, of the data DQdata
1
to DQdata
4
input to the data transfer block, the data DQdata
1
, which is output from the cell array block
101
in the chip peripheral portion, takes effect as the output data Dout data last.
On the other hand, the data DQdata
1
to DQdata
4
input to the data transfer block are each loaded at the same rising edge of the control clock CLK, that is, these data each use the same loading timing.
Thus, the data DQdata
1
, which is output from the cell array block
101
in the chip peripheral portion, has the smallest loading timing margin.
In
FIG. 1
, operational timings for the transfer block
16
will be considered by assuming that a significant signal delay occur in word lines in the cell array blocks
101
to
104
, which are selectively driven by the row decoder
11
, and that the amount of time required for the data DQdata
1
output from the cell array block
101
in the chip peripheral portion to reach the data line buffer
131
substantially differs from the amount of time required for the data DQdata
4
output from the cell array block
104
in the chip central portion to reach the data line buffer
144
.
In this case, a data loading period T following a certain rising edge of the control clock CLK is considered. As shown in
FIGS. 3A
to
3
E, of the data DQdata
1
to DQdata
4
input to the data transfer block
16
, the DQdata
2
to DQdata
4
are loaded in

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