Clock synchronization method

Details Clock synchronization method Clock synchronization method

1998-12-21

2002-01-08

Deppe, Betsy L. (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S371000, C327S141000, C327S156000

Reexamination Certificate

active

06337891

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a clock synchronization method by using a digital processing phase locked loop(DP-PLL); and, more particularly, to a clock synchronization method capable of attenuating jitter included in a reference clock.
DESCRIPTION OF THE PRIOR ART
Phase Locked Loops(PLL's) are found in a myriad of electronic applications, such as communication receivers and clock synchronization circuits in computer systems, for providing a reference clock with a known phase for clocking incoming and outgoing data. A conventional charge pump PLL comprises a phase detector for monitoring the phase difference between an input clock signal and an output signal from a voltage controlled crystal oscillator (VCXO) and generating an up control signal and a down control signal for a charge pump circuit which charges and discharges a loop filter at the input of the VCXO. The up and down control signals increase and decrease the VCXO output frequency, respectively, to maintain a predetermined phase relationship between signals applied to the phase detector, as is well known.
A common problem with conventional PLL's is the occurrence of a phase jitter at the output of the VCXO. When the phase difference between the output signal of the VCXO and the input clock signal becomes less than the resolution of the PLL, the phase detector continuously corrects the VCXO for the perceived phase error. Thus, the output signal from the VCXO jumps back and forth between a phase lead and a phase lag with respect to the input clock signal. Such a phase jitter reduces the effective bandwidth of the PLL since the output edge location of the output signal from the VCXO continuously changes. Therefore, the phase of the output signal of the VCXO is accurate only within the jitter window.
A PLL circuit is disclosed in U.S. Pat. No. 5,126,693 issued to William et al. in order to overcome this problem. The William et al. is directed to a phase locked loop reducing output phase jitter by averaging an input clock signal and a delayed input clock signal. A control signal selects one of the input clock signal and the delayed input clock signal for providing a reference clock signal for the phase locked loop. The output oscillator signal of the PLL is divided by a predetermined integer value for providing the control signal to select either one of the input clock signal and the delayed input clock signal. The PLL establishes a phase lock to the input clock signal during a first state of the control signal and then establishes a phase lock to the delayed input clock signal during a second state of the control signal such that the average value of the output signal of the PLL is substantially constant.
Although the PLL devised by William et al. generates a substantially constant output by selectively applying an input clock signal or a delayed input clock signal as a reference signal, it is still required to develop a more efficient algorithm to cope with the problem resulting from the phase jitter.
SUMMARY OF THE INVENTION
It is, therefore, a primary object of the invention to provide a clock synchronization method capable of attenuating jitter included in a reference clock.
In accordance with one aspect of the present invention, there is provided a clock synchronization method for generating a system clock of a predetermined frequency with reference to a reference clock, comprising the steps of: (a) receiving the reference clock, the system clock and a divided clock having a same frequency as that of the reference clock, wherein the divided clock is obtained by dividing the system clock by a predetermined integer; (b) obtaining phase deviations between the reference clock and the divided clock, a phase deviation being the number of periods of the system clock in a section between a rising edge of the reference clock and a nearest rising edge of the divided clock; (c) averaging consecutive phase deviations to thereby generate an average phase deviation of a 3rd order, wherein the number of averaged consecutive phase deviations varies with the phase jitter characteristics of the reference clock; and (d) controlling the frequency of the system clock based on the average phase deviation of the 3rd order.


REFERENCES:
patent: 4498059 (1985-02-01), Edwards et al.
patent: 5373255 (1994-12-01), Bray et al.
patent: 6154511 (2000-11-01), Nakamura et al.
patent: 6188739 (2001-02-01), Everitt et al.

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