Clock synchronization circuit and semiconductor device...

Details Clock synchronization circuit and semiconductor device... Clock synchronization circuit and semiconductor device...

2001-01-11

2002-05-07

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000

Reexamination Certificate

active

06385126

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductor devices and, in particular, to a clock synchronization circuit and a semiconductor device having the same.
BACKGROUND DESCRIPTION
The operating speed of a central processing unit (CPU), which is a signal processing unit, has been radically improved over the last several years. However, the operating speed of dynamic random access memory (DRAM) semiconductor devices, which correspond to the main memory of a CPU, has not been greatly improved. Rather, it has been identified as a main bottle-neck factor of computer systems. To reduce the difference in operating speed between a CPU and a DRAM semiconductor device, new DRAM semiconductor devices are being developed such as synchronous DRAM (SDRAM) semiconductor devices, Rambus DRAM semiconductor devices, synclink DRAM semiconductor devices, and so forth. These DRAM semiconductor devices have a feature such that data received from an external source or output to the outside is processed in synchronization with an internal clock. The internal clock is generated from an external clock signal which is received from an external source. A circuit which synchronizes the internal clock signal with the external clock signal is referred to as a clock synchronization circuit. A phase locked loop and a delay locked loop are included in the clock synchronization circuit. Among them, the delay locked loop is usually used in the DRAM semiconductor devices.
FIG. 1
is a block diagram of a clock synchronization circuit
101
according to the prior art. Referring to
FIG. 1
, the clock synchronization circuit
101
has a dual loop structure having a core delay locked loop
111
and a peripheral delay locked loop
113
. The core delay locked loop
111
receives an external clock signal inCLK and generates 6 sub clock signals CK
1
through CK
6
(hereinafter collectively referred to as “CK
1
-CK
6
”). The sub clock signals CK
1
-CK
6
have a predetermined phase difference. The peripheral delay locked loop
113
receives the sub clock signals CK
1
-CK
6
, generates a clock signal Q, and synchronizes the clock signal Q with an external clock signal inCLK using a phase interpolation technique. The peripheral delay locked loop
113
includes a phase selector
121
, a selection phase transformer
131
, a phase interpolator
141
, a phase detector
151
and a controller
161
. The phase interpolator
141
interpolates the phases of signals &PHgr;′ and &PSgr;′ output from the selective phase transformer
131
to generate the clock signal Q. The phase interpolator
141
receives 16 bits of signals output from the controller
161
in order to determine the degree of interpolation of the phase of the clock signal Q.
The phase interpolation technique used by the conventional clock synchronization circuit
101
can achieve its effects when the slew rate of an external clock signal inCLK is small, or when a smaller phase boundary can be provided by increasing the number of sub-clock signals CK
1
-CK
6
generated by the core delay locked loop
111
. However, in the former case, the dynamic noise sensitivity of the clock synchronization circuit
101
is increased, so that jitter performance is degraded. In the latter case, a burden on the clock synchronization circuit
101
is increased.
Accordingly, it would be desirable and highly advantageous to have a clock synchronization circuit having improved jitter performance.
SUMMARY OF THE INVENTION
The problems stated above, as well as other related problems of the prior art, are solved by the present invention, a clock synchronization circuit and a semiconductor device having the same. Both the clock synchronization circuit and semiconductor device have improved jitter performance with respect to prior art devices.
According to a first aspect of the invention, there is provided a clock synchronization circuit for synchronizing an external clock signal with an internal clock signal. The circuit is connected to a clock buffer adapted to output the internal clock signal. The circuit includes: a first loop adapted to receive the external clock signal and output a plurality of reference clock signals having a predetermined phase difference therebetween; and a second loop adapted to delay the plurality of reference clock signals, select a signal from among the plurality of delayed reference clock signals, provide the selected signal to the clock buffer, detect a phase difference between the internal clock signal output from the clock buffer and the external clock signal, generate a plurality of control voltages to reduce the detected phase difference, and control a delay amount of each of the plurality of reference clock signals in response to the plurality of control voltages, so as to synchronize the internal clock signal with the external clock signal.
According to a second aspect of the invention, there is provided a clock synchronization circuit for synchronizing an external clock signal with an internal clock signal. The circuit is connected to a clock buffer. The circuit includes: a first loop adapted to receive the external clock signal and output first through fourth reference clock signals, consecutive pairs of the first through fourth reference clock signals having a 90° phase difference therebetween; and a second loop having first through fourth voltage control delay units adapted to delay the first through fourth reference clock signals, the second loop adapted to select a reference clock signal from among the first through fourth delayed reference clock signals, provide the selected reference clock signal to the clock buffer for conversion to the internal clock signal, detect a phase difference between the internal clock signal output from the clock buffer and the external clock signal, generate a plurality of control voltages having different levels according to the detected phase difference to reduce the detected phase difference, provide the plurality of control voltages to the first through fourth voltage control delay units, and control the delay amount of the selected reference clock signal in response to a control voltage from among the plurality of control voltages, so as to synchronize the internal clock signal with the external clock signal.
According to a third aspect of the invention, a level of the control voltage applied to a voltage control delay unit among the first through fourth voltage control delay units that outputs the selected reference clock signal is different from levels of other control voltages from among the plurality of control voltages applied to other voltage control delay units among the first through fourth voltage control delay units that generate unselected reference clock signals.
According to a fourth aspect of the invention, delay amounts applied to the first through fourth reference clock signals are always detected, the selected reference clock signal is switched to an unselected one of the first through fourth delayed reference clock signals having a phase that lags a phase of the selected reference clock signal by 90° when the delay amount of the selected reference clock signal approaches a maximum value, and the selected reference clock signal is switched to an unselected one of the first through fourth delayed reference clock signals having a phase that leads the phase of the selected reference clock signal by 90° when the delay amount of the selected reference clock signal approaches a minimum value.
According to a fifth aspect of the invention, there is provided a clock synchronization circuit for synchronizing an external clock signal with an internal clock signal. The circuit is connected to a clock buffer. The circuit includes: a first loop adapted to receive the external clock signal and output a first and a second reference clock signal, the reference clock signals being differential signals having a 90° phase difference therebetween; and a second loop having a first voltage control delay unit adapted to delay the first reference clock signal to output a first and a second di

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