Clock synchronization circuit and clock synchronizing method in

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

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375330, 375332, 375354, 375355, H04L 700, H04L 2722, H03D 322

Patent

active

055352529

ABSTRACT:
A clock synchronization circuit for use in a baseband demodulator of communication equipment of a digital modulation type, in which detection data is subjected to an interpolating operation with respect to at least one point between adjacent two sample values of the detection data, subjected to a conversion into one-bit data indicative of a positive or negative value, and then passed through a one-bit-input band pass filter to perform phase error detection. Consequently, clock synchronization accuracy is improved while preventing a sampling rate and circuit scale from being made large.

REFERENCES:
patent: 4392234 (1983-07-01), Maruta
patent: 4411006 (1983-10-01), Horna
patent: 4707841 (1987-11-01), Yen et al.
patent: 5077531 (1991-12-01), Takeuchi et al.
patent: 5187719 (1993-02-01), Birgenheier et al.
patent: 5235622 (1993-08-01), Yoshida
patent: 5309484 (1994-05-01), McLane et al.
patent: 5365468 (1994-11-01), Kakubo et al.

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