Electrical computers and digital processing systems: support – Clock control of data processing system – component – or data...
Reexamination Certificate
2001-05-14
2004-09-21
Lee, Thomas (Department: 2115)
Electrical computers and digital processing systems: support
Clock control of data processing system, component, or data...
C713S503000, C375S271000
Reexamination Certificate
active
06795932
ABSTRACT:
FIELD OF THE INVENTION
The present invention in general relates to a clock switchover circuit. In particular, this invention relates to a clock switchover circuit for switching a signal level of, for example, as a CPU of a microcomputer.
BACKGROUND OF THE INVENTION
A conventional clock switchover circuit is shown in FIG.
4
. This clock switchover circuit is disclosed in the Japanese Patent Application Laid-Open (JP-A) No. 5-100766. The conventional clock switchover circuit
100
includes a clock signal selection section having 3-input AND circuits
210
and
220
and an OR circuit
230
.
The clock switchover circuit
100
also includes D flip-flops (“DFF”)
140
and
150
. Signals output from the DFF
140
and
150
and a clock signal clkY are input into the AND circuit
210
. The clock switchover circuit
100
further includes DFF
190
and
200
. Signals output from the DFF
190
and
200
and a clock signal clkX are input into the AND circuit
220
.
The clock switchover circuit
100
further includes AND circuits
110
and
160
. The AND circuit
110
is supplied with a selection signal selX. A signal output from this AND circuit
110
is supplied to the DFF
140
. The AND circuit
160
is also supplied with the selection signal selX. A signal output from this AND circuit
160
is supplied to the DFF
190
.
The conventional clock switchover circuit
100
functions as explained below.
FIG. 5
is a time chart of the clock switchover circuit
100
. As shown in
FIG. 5
, the clock signal clkY is selected as an output signal OUT before time t0.
At the time t0, the selection signal selX is changed from “L” (a low logical level) to “H” (a high logical level) At time t1, output states of the DFF
140
,
150
,
190
and
200
become “L”, “L”, “L” and “H”, respectively, and the clock signal clkY disappears from the output signal OUT.
At time t2, the output states of the DFF
140
,
150
,
190
and
200
become “L”, “L”, “L” and “L”, respectively, and the clock signal clkY does not appear as the output signal OUT.
At time t3, the output states of the DFF
140
,
150
,
190
and
200
become “H”, “L”, “L” and “L”, respectively, and the clock signal clkY does not appear as the output signal OUT.
At time t4, the output states of the DFF
140
,
150
,
190
and
200
become “H”, “H”, “L” and “L”, respectively, and the clock signal clkY does not appear as the output signal OUT.
Thus, switchover of the clock signal clkY to clkX occurs by output cessation of the clock signal clkY at the time t1, generation of a blank interval corresponding to one clock of the clock signal clkY in a time interval between the time t1 and t2, generation of a blank interval corresponding to one clock of the newly selected clock signal clkX in a time interval between the time t3 and t4, and output of the clock signal clkX at the time t4.
In the conventional clock switchover circuit, therefore, it is necessary to generate many blank intervals in order to prevent glitches caused by collision of switched clock signals. These intervals are a hindrance to fast access.
In addition, since the clock signal selection section includes 3-input gates, the signal transfer efficiency degrades.
In addition, hazards are apt to be caused by dispersion of floating delays. Thus, there is a problem that a racing phenomenon may occur between DFFs.
SUMMARY OF THE INVENTION
The clock switchover circuit according to one aspect of this invention comprises a first inverter circuit which is supplied with a clock switchover signal, and a NAND circuit which is supplied with an output of the first inverter circuit. Further, there is provided a first flip-flop which is supplied with an output of the NAND circuit at a data input terminal thereof, supplied with a first clock input signal at a clock input terminal thereof, and supplied with a system reset signal at a reset terminal thereof. Further, there is provided a NOR circuit which is supplied with the output of the first inverter circuit. Further, there is provided a second flip-flop which is supplied with an output of the NOR circuit at a data input terminal thereof, supplied with a second clock input signal at a clock input terminal thereof, and the system reset signal at a reset terminal thereof. Further, there is provided a second inverter circuit which is supplied with an output of an output inversion signal terminal of the first flip-flop. Further, there is provided a clock signal selection section which is supplied with an output of the second inverter circuit, the first clock input signal, an output of an output inversion signal terminal of the second flip-flop, and the second clock input signal. Further, there is provided a third inverter circuit, which is supplied with a signal output signal from the clock signal selection section, and which outputs a clock signal.
The clock switchover circuit according to another aspect of this invention comprises a first switch for conducting switchover to select a power supply potential terminal or a ground potential terminal according to the level of the clock switchover signal. Further, there is provided a second switch for conducting switchover to select a first clock input signal terminal or a second clock input signal terminal according to a level of a clock switchover signal. Further, there is provided a shift register which is supplied with a potential selected by the first switch at a data input terminal thereof, supplied with a clock input signal selected by the second switch at a clock input terminal thereof, and supplied with a system reset signal at a reset terminal thereof, the shift register outputting a shifted level from a data output terminal thereof. Further, there is provided a switchover section supplied with a signal output from the shift register, the first clock input signal, the second clock input signal, and the system reset signal.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.
REFERENCES:
patent: 4870299 (1989-09-01), Chen
patent: 5155380 (1992-10-01), Hwang et al.
patent: 5274678 (1993-12-01), Ferolito et al.
patent: 5623223 (1997-04-01), Pasqualini
patent: 5652536 (1997-07-01), Nookala et al.
patent: 60-251418 (1985-12-01), None
patent: 63000726 (1988-01-01), None
patent: 5-100766 (1993-04-01), None
Rosing et al, Clock Switching: a New Design for current Testability (DcT) Method for Dynamic Logic Circuits, IEEE, Nov. 1998, p. 6.
Lee Thomas
Leydig , Voit & Mayer, Ltd.
Renesas Technology Corp.
Suryawanshi Suresh K
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