Clock supply circuit and clock supply method

Details Clock supply circuit and clock supply method Clock supply circuit and clock supply method

2007-08-21

2010-12-21

Vo, Don N (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

Reexamination Certificate

active

07856075

ABSTRACT:
The present invention provides a clock supply device and a clock supply method by which the holdover characteristics that maintains with high precision the same frequency as the frequency observed immediately before an error can be achieved simply with the addition of a high stability oscillator. An output clock signal that is output from a conventional PLL circuit is monitored with a clock signal of a high-stability fixed oscillator, and the monitor result is written in a memory. A holdover reference generating circuit averages the result written over a certain period of time. When a frequency error monitoring circuit detects a frequency error in an input reference signal, a selector selects a holdover reference, instead of the input reference signal, and inputs the holdover reference to the PLL circuit. Alternatively, the holdover reference generating circuit may select the input of the PLL circuit at the time of an error, and then perform holdover.

REFERENCES:
patent: 5260979 (1993-11-01), Parker et al.
patent: 5530389 (1996-06-01), Rieder
patent: 5572167 (1996-11-01), Alder et al.
patent: 6687322 (2004-02-01), Zhang et al.
patent: 2002232407 (2002-08-01), None
patent: 97/20393 (1997-06-01), None
European Patent Office issued an European Office Action dated Jul. 2, 2009, Application No. 07 144 599.9.

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