Clock skew reduction using spider clock trace routing

Details Clock skew reduction using spider clock trace routing Clock skew reduction using spider clock trace routing

1996-12-31

1999-01-19

Santamauro, Jon

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326101, H03K 1900

Patent

active

058617647

ABSTRACT:
A technique for reducing skew between clock signals in a digital system requiring multiple clock signals. The system preferably is implemented on a printed circuit board. An oscillator circuit provides a periodic signal to a clock buffer which generates multiple periodic clock signals. The clock signals are provided to various destination points on the printed circuit board. The rising and falling edges of each clock signal generated by the clock buffer do not occur precisely at the same time as the rising and falling edges of the other clock signals. This misalignment of clock edges, or skew, is detrimental to system performance, but is reduced substantially by connecting all of the clock buffer's output clock signals together at a single physical point or node. Accordingly, the printed circuit board traces carrying each of the clock signals are routed to a single point node. A single point node is used to reduce skew caused by the clock buffer. Single point nodes also may be used at various locations on the printed circuit board to reduce skew caused by differences in the lengths of the traces carrying the clock signals.

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patent: 5239215 (1993-08-01), Yamaguchi
patent: 5396129 (1995-03-01), Tabira
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patent: 5523920 (1996-06-01), Machuga et al.
patent: 5537061 (1996-07-01), Honjo
patent: 5686845 (1997-11-01), Erdal et al.

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