Clock skew reduction using active shields

Details Clock skew reduction using active shields Clock skew reduction using active shields

2002-05-24

2004-03-16

Thompson, A. M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C257S659000

Reexamination Certificate

active

06708314

ABSTRACT:

BACKGROUND OF INVENTION
A typical computer system includes at least a microprocessor and some form of memory. The microprocessor has, among other components, arithmetic, logic, and control circuitry that interpret and execute instructions necessary for the operation and use of the computer system.
FIG. 1
shows a typical computer system (
10
) having a microprocessor (
12
), memory (
14
), integrated circuits (
16
) that have various functionalities, and communication paths (
18
), i.e., buses and wires, that are necessary for the transfer of data among the aforementioned components of the computer system (
10
).
A clock signal is critical to the operation of a microprocessor-based computer system. The clock signal initiates and synchronizes the operation of almost all of the components of the typical computer system. As computers operate at increasing clock speeds, it becomes critical to ensure that clock signals on a microprocessor are provided to various logic elements on the microprocessor in an accurate and timely manner.
FIG. 2
shows a clock distribution network (
20
) for a microprocessor (
12
).
A reference clock (also known in the art as “system clock” and shown in
FIG. 2
as ref_clk), which is typically generated from outside the microprocessor (
12
), serves as an input to a phase locked loop (“PLL”) (
15
). Essentially, the PLL (
15
) uses feedback to maintain a specific phase relationship between its output (shown in
FIG. 2
as chip_clk) and the reference signal. The chip clock from the PLL (
15
) is then distributed to one or more clock drivers/buffers (
17
), which, in turn, distribute the chip clock to a global clock grid (
19
), where the global clock grid (
19
) feeds the chip clock to various microprocessor components such as local clock grids (
24
) and a feedback loop (
26
) that feeds the chip clock back to the PLL (
14
). The local clock grids (
24
) feed the chip clock to base components of the microprocessor (
12
), such as latches (
22
) and flip-flops (
28
). However, due to one or more types of variations across the microprocessor, a particular clock signal may arrive at different parts of the chip at different times. The difference in the arrival of a clock signal at different logic elements due to system variations is referred to and known in the art as “clock skew.”
Microprocessors are often fabricated on an integrated circuit (IC). Because signal wires within an IC are often in close proximity to each other, e.g., the signal wires driven by clock drivers/buffers (
17
) have a propensity to affect the behavior of each other. This occurs due to intrinsic capacitances (also referred to and known as “cross-coupling capacitance”) that are formed between signal wires operating at different voltage levels. For example, some amount of cross-coupling capacitance is likely to be formed between two signal wires that are located relatively close to one another. If a voltage on one of the two signal wires changes, the cross-coupling capacitance will have a tendency to adversely affect the other signal. For example, when the voltage is raised on one of the two signal wires, i.e., transitioning to a “logic high,” the cross coupling capacitance will tend to raise the voltage on the other signal wire, and when the voltage is reduced on one of the two signal wires, i.e., transitioning to a “logic low,” the cross coupling capacitance will tend to reduce the voltage on the other signal wire. In other words, when one of the signal wires switches state, noise may be injected on the other signal, causing the other signal to glitch, i.e., an electrical spike occurs. Such undesired behavior on the non-switching signal may lead to performance degradation because the noise injected on the non-switching signal can propagate to other parts of the processor causing timing failures and/or circuit malfunction.
An approach that designers have used to combat such cross-coupling capacitance induced behavior involves the use of wire shielding technique, which involves placing shield wires adjacent to a signal wire (“shielding” the signal wire from other signals). The shield wires may maintain constant voltage. To this end,
FIG. 3
shows a typical wire shielding technique. In
FIG. 3
, a logic stage (e.g., clock driver/buffer (
17
)) outputs on a signal wire (
23
) that is shielded by a first shield wire (
25
) and a second shield wire (
26
), where the first shield wire (
25
) is connected to logic high, i.e., a voltage source (
29
), and the second shield wire (
26
) is connected to logic low, i.e., ground (
33
). The clock driver/buffer (
17
) is also connected to the voltage source (
35
) and ground (
39
), respectively; however, the voltage source (
35
) and ground (
39
) of the logic stage (
17
) may be different from the voltage source (
29
) and ground (
33
) of the shield wires (
25
,
26
). In any event, the placement of the shield wires (
25
,
26
) cause capacitances (
35
,
37
) to develop between the respective shield wires (
25
,
26
) and the signal wire (
23
).
Because of such a wire shielding technique, other signals in close proximity to the signal wire (
23
) are not affected by the switching behavior of the signal wire (
23
) due to the fact that the signal wire (
23
) is shielded by shield wires (
25
,
26
) that have constant values while the signal wire (
23
) is able to transition between high and low. Alternatively, the wire shielding technique lessens the effects of the switching behavior of other signals (not shown) on the signal wire (
23
) that are in close proximity to the signal wire (
23
). Typically, clock signals are shielded due to the close proximity of signal wires within an IC. This provides noise immunity to and from the clock signals.
Changes in the voltage value of the clock signal create charging and discharging events in capacitors associated with the signal wire on which the clock signal propagates. A capacitor with a potential difference across its terminals is considered to be a charged capacitor, and a capacitor with no potential difference across its terminals is considered to be a discharged capacitor. Therefore, a charging event is described as a process by which an increase in potential difference is induced across the terminals of a capacitor by delivering charge to the capacitor. A discharging event is described as a process by which a decrease in potential difference is induced across the terminals of a capacitor by removing the charge stored in the capacitor.
FIG. 4
shows an exemplary timing diagram corresponding to the wire shielding technique in FIG.
3
. The behavior of the input signal of the clock signal, the output signal of the first shield wire (
25
), the output signal of the second shield wire (
26
), and the output signal of the signal wire (
25
) are given. The clock signal transitions between two voltage levels (high to low or low to high), the shield wires (
25
,
26
) maintain a constant voltage of high and low, respectively, and the signal wire (
23
) outputs a copy of the clock signal with a delay of t
1
, some finite measure of time. The rise and fall time of the output signal of the signal wire (
23
) is slow compared to the clock signal as a result of characteristics of the logic stage (e.g., clock driver/buffer (
17
)) driving the clock signal, indicated by the sloped edges of the output signal of the signal wire (
23
).
Referring to
FIG. 3
, when the clock signal is high, the signal wire (
23
) is high, the second shield wire (
26
) is low, and the first shield (
25
) wire is high. There is no potential difference between the first shield wire (
25
) and the signal wire (
23
), therefore capacitors (
35
) are considered discharged; furthermore, there is a potential difference between the second shield wire (
26
) and the signal wire, (
23
) therefore capacitors (
37
) are considered charged.
When the clock signal is low, the signal wire (
23
) is low, the second shield wire (
26
) is low, and the first shield (
25
) wire is high. There is no potential difference between the second shield wire (
26

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