Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2005-08-09
2005-08-09
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S094000, C327S099000, C327S298000, C327S407000, C375S354000, C375S355000, C375S360000
Reexamination Certificate
active
06927604
ABSTRACT:
A clock signal selector circuit is disclosed including a synchronizer circuit, two switching circuits, and a multiplexer. The synchronizer circuit synchronizes a first control signal to a first clock signal, thereby producing a second control signal. A first switching circuit produces the first clock signal at a first node when the second control signal is asserted. The multiplexer drives a second node with a signal at the first node when the second control signal is asserted. The second switching circuit forms an electrical connection between the first and second nodes when the second control signal is deasserted. The two switching circuits significantly reduce a probability of error at the second node due to metastability when the second control signal transitions from asserted to deasserted and the first clock signal is deselected. The second switching circuit provides electrical feedback from the second node to the first node.
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Rabaey, Jan;Digital Integrated Circuits: ADesign Perspective; pp. 533-537; Prentice Hall (1996).
Boerstler David W.
Hailu Eskinder
Carr LLP
Gerhardt Diana R.
Tan Vibol
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