Clock signal reproduction circuit and data reproduction circuit

Details Clock signal reproduction circuit and data reproduction circuit Clock signal reproduction circuit and data reproduction circuit

1994-12-22

1998-11-10

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

331 1A, 331 14, 331 17, H03D 3246

Patent

active

058355448

ABSTRACT:
A clock signal reproduction circuit including an A/D conversion circuit for converting an input RF analog signal with a restricted upper limit of a frequency band into a digital signal, a digital phase error calculation unit for digitally calculating a phase error of a digital signal converted in the A/D conversion circuit, a control voltage generating unit including a loop filter, a D/A conversion unit for outputting an analog control voltage signal based on the digital phase error calculated, and an analog voltage-controlled type oscillating circuit for outputting a reproduction clock signal having a frequency of at least 2 times the frequency of the input analog signal. The A/D conversion circuit uses the clock signal output from the analog voltage-controlled type oscillating circuit to convert the input analog signal into a digital format and output a reproduction clock signal from the analog voltage-controlled oscillating circuit.

REFERENCES:
patent: 4330863 (1982-05-01), Wright
patent: 4339731 (1982-07-01), Adams
patent: 4672447 (1987-06-01), Moring et al.
patent: 4929918 (1990-05-01), Chung et al.
patent: 5057794 (1991-10-01), Shih
patent: 5425060 (1995-06-01), Roberts et al.

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