Clock signal networks for structured ASIC devices

Details Clock signal networks for structured ASIC devices Clock signal networks for structured ASIC devices

2008-07-22

2008-07-22

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

11141867

ABSTRACT:
Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served from that predetermined location.

REFERENCES:
patent: 7194718 (2007-03-01), Sano et al.
patent: 2006/0164121 (2006-07-01), Or-Bach et al.
patent: 2006/0247875 (2006-11-01), Ooshima
U.S. Appl. No. 10/884,460, Chua et al.
U.S. Appl. No. 11/097,633, Schleicher et al.

Affiliated with

Also associated with

Rating

Clock signal networks for structured ASIC devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock signal networks for structured ASIC devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock signal networks for structured ASIC devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3940982