Clock signal generator

Details Clock signal generator Clock signal generator

1999-10-05

2001-07-10

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S052000

Reexamination Certificate

active

06259274

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a clock signal generator for generating a clock signal used for digital information equipment and so forth. More to particularly this invention relates to a clock signal generator which enables change of duty ratio of the clock signal to be inhibited.
DESCRIPTION OF THE PRIOR ART
A clock signal with fixed cycle often operates as a basis of various kinds of internal timing in internal circuits of the conventional digital information equipment. Such the clock signal possesses a duty ratio of approximately degree of 50% immediately after generation. Change of the duty ratio from value of degree of 50% occurs according to various kinds of causes. Such the causes are various kinds of capacitance added by delay on transmission line of substrate wiring of the device or connection of various kinds of gate circuit and/or change of power source voltage level. Under the situation, there are proposed some clock signal generators for inhibiting change of duty ratio caused by various kinds of causes of such the clock signals.
FIG. 1
shows an outline of configuration of a clock signal generator proposed conventionally. In the clock signal generator
10
, an input clock signal
11
is inputted both to a leading detector
12
, and a frequency multiplier
13
. When a leading of the input clock signal
11
is detected by the leading detector
12
, a leading detection signal
14
of pulse shaped waveform is outputted therefrom. This pulse shaped waveform of the leading detection signal
14
is inputted to a delay circuit
15
. A delayed signal
16
is delayed by the delay circuit
15
only fixed time. The delayed signal
16
delayed by the delay circuit
15
only fixed time is inputted to one side of input terminal of 2-input NAND circuit
17
. Further, the input clock signal is multiplied by a frequency multiplier
13
in order to generate a multiplied signal
18
. The multiplied signal
18
is inputted to a clock input terminal (CK) of a Delayed Flip-Flop
19
(herein after referring to D-FF) with a set terminal. An inversion output signal
20
outputted from an inversion output terminal (Q(−)) of the D-FF
19
is inputted to the data input terminal (D) and the another input terminal different from a terminal to which the delayed signal
16
is inputted in the 2-input NAND circuit
17
. An output signal
21
of the 2-input NAND circuit
17
is inputted to the set input terminal (S). An output clock signal
22
is outputted from an output terminal (Q) of the D-FF
19
. In the D-FF
19
, when the output signal of “L” level from the 2-input NAND circuit
17
is inputted to the set input terminal (S), the output clock signal
22
outputted from the output terminal (Q) is set to “H” level, and the inversion output signal
20
outputted from the inversion output terminal (Q(−)) is set to “L” level.
The leading detection circuit
12
is provided with an inverter
24
(hereinafter referring to INV
24
) which outputs the inversion clock signal
23
that logic of the input clock signal
11
is inverted, and an AND circuit
25
in which the input clock signal is inputted to one side of input terminal thereof and the inversion clock signal
23
is inputted to the another side of input terminal thereof. The leading detection signal
14
is outputted as a pulse signal having width corresponding to only delay time of the INV circuit
24
, while being synchronized with leading of the input clock signal according to such constitution of the leading detection circuit
12
. The delay circuit
15
is provided with delay cells
26
, and
27
for delaying inputted signal with every fixed time. The delayed signal
16
is obtained in such a way that the delay cells
26
, and
27
cause the leading detection signal
14
to be delayed corresponding to only prescribed time. The frequency multiplier
13
is capable of frequency multiplying the input clock signal by two times.
FIGS. 2A
to
2
G indicate appearance of change of the signal in respective sections of this device.
FIG. 2A
indicates signal waveform of the clock input signal
11
.
FIG. 2B
indicates signal waveform of the leading detection signal
14
.
FIG. 2C
indicates signal waveform of the delayed signal
16
.
FIG. 2D
indicates signal waveform of the frequency multiplied signal
18
.
FIG. 2E
indicates signal waveform of the output signal
21
.
FIG. 2F
indicates signal waveform of the output clock signal
22
.
FIG. 2G
indicates signal waveform of the inversion output signal
20
. Here, the input clock signal
11
whose duty ratio is not held 50% is inputted under the condition of prescribed cycle as shown in FIG.
2
A. The leading detection circuit
12
detects a leading of the input clock signal
12
inputted in such the way, thus outputting the leading detection signal
14
with pulse shaped waveform having width corresponding to delay time of the above-described INV circuit
24
as shown in FIG.
2
B. The leading detection signal
14
is delayed only prescribed time by the delay circuit
15
as shown in FIG.
2
C. On the other hand, the frequency multiplier
13
frequency multiplies the input clock signal
11
by two times of original frequency in order to output frequency multiplied signal
18
whose frequency is two times of the original frequency as shown in FIG.
2
D.
The D-FF
19
functions as a Toggle Flip-Flop (hereinafter referring to T-FF) synchronized with the frequency multiplied signal
18
because the inversion output signal
20
is inputted to the data input terminal (D). According to this operation, the D-FF
19
inverts an output logic in every input of the frequency multiplied signal
18
, thus the D-FF
19
functions as a frequency dividing circuit for the frequency multiplied signal
18
. On the other hand, the D-FF
19
which frequency divides the frequency multiplied signal
18
outputs the output clock signal
22
. When a phase of the leading of this output clock signal
22
of the D-FF
19
is different from a phase of the leading of the input clock signal
11
by 180 degrees, the output signal
21
as shown in
FIG. 2E
is outputted as a negative pulse from the 2-input NAND circuit
17
. The output clock signal from the D-FF
19
is fixed to “H” level in spite of the frequency multiplied signal
18
in order to harmonize both phases with each other. Subsequently, the D-FF
19
generates the output clock signal
22
(
FIG. 2F
) whose output is inverted in every input of the frequency multiplied signal
18
and the inversion output signal
20
(FIG.
2
G). Thus it is capable of being generated the clock signal with duty ratio 50 %, whose phase is harmonized with that of the input clock signal.
Technology with regard to such the clock signal generator is disclosed in, for instance, the Japanese Patent Application Laid-Open No. HEI 4-240915 “Clock Signal Phase Establishment Circuit”.
However, in such the conventional clock signal generator, there is the problem that it is incapable of being harmonized the input phases with each other when the input clock signal whose leading becomes dull is inputted. Namely, when the leading of the input clock signal
19
becomes dull, it is incapable of being generated set signal for the sake of phase harmonization to be inputted to the D-FF
19
with prescribed timing. Thus, in recent year, when a clock signal is transferred to another device through one device, leading edge or trailing edge of a clock signal becomes dull. For that reason, in some cases, another device to which the output clock signal is inputted does not operate accurately. Further, in design of the above described frequency multiplier or delay circuit, man-hour of design and manufacturing increase because manufacturing condition and so forth should be considered.
In particular, with high speed tendency of the clock signal of late years, in case where the clock signal is inputted through level comparator with high speed operation from external section, change in edge of the clock signal of an open collector output or open drain output becomes dull

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