Clock signal generation circuits and methods using phase...

Details Clock signal generation circuits and methods using phase... Clock signal generation circuits and methods using phase...

2007-02-13

2007-02-13

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S163000, C327S291000

Reexamination Certificate

active

11066072

ABSTRACT:
A clock signal generation circuit includes a Delay Locked Loop (DLL) that, responsive to an input clock signal and first and second feedback clock signals, generates a plurality of phased clock signals time-shifted with respect to one another. The clock signal generation circuit further includes a phase mixer that receives the plurality of phased clock signals, that phase mixes first and second groups of the plurality of phased clock signals to generate the respective first and second feedback signals, and that phase mixes the first and second feedback signals to generate an output clock signal. The phased plurality of clock signals may be separated by substantially uniform delays, the first group of clock signals may include signals delayed even numbers of delays with respect to the input clock signal, and the second group of clock signals may include signals delayed odd numbers of delays with respect to the input clock signal. Each of the substantially uniform delays may be approximately one-half of a period of the input clock signal.

REFERENCES:
patent: 6466071 (2002-10-01), Kim et al.
patent: 6768361 (2004-07-01), Kwak
patent: 6897693 (2005-05-01), Kim
patent: 6956418 (2005-10-01), Kwak et al.
patent: 6963235 (2005-11-01), Lee
patent: 7016452 (2006-03-01), Partsch et al.
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patent: 2001-094529 (2001-11-01), None
patent: 10-2003-0002436 (2003-01-01), None
patent: 10-2003-0090129 (2003-11-01), None
patent: 2003-090129 (2003-11-01), None
Notice to Submit a Response for Korean Patent Application No. 10-2004-0013009 mailed on Sep. 28, 2005.

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