Clock signal generation circuit capable of operating at high spe

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

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331 1A, 331 14, 331 18, 331 25, 331 34, H03D 324, H03L 700

Patent

active

055770860

ABSTRACT:
A clock signal generation circuit performs a stable operation with respect to both a high frequency input clock signal and a sufficient low frequency testing clock signal. The circuit includes a phase comparator for generating a phase difference output corresponding to a phase difference between an internal clock signal and a reference clock signal externally supplied; a frequency distinction circuit for generating a frequency change-over signal when a frequency of the reference clock signal is lower than a preset reference signal; a loop filter for generating an output voltage corresponding to the phase difference output and for changing over a filter constant to that for a low frequency corresponding to the frequency change-over signal; and a voltage control oscillator for setting a frequency of the internal clock signal to a frequency corresponding to the output voltage of the loop filter and for decreasing a change amount of an oscillating frequency with respect to an input signal corresponding to the frequency change-over signal.

REFERENCES:
patent: 5202906 (1993-04-01), Saito et al.
patent: 5272453 (1993-12-01), Traynor et al.
patent: 5285483 (1994-02-01), Ogawa et al.
patent: 5304955 (1994-04-01), Atriss et al.
patent: 5410571 (1995-04-01), Yonehawa et al.
patent: 5410572 (1995-04-01), Yoshida

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