Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2001-12-26
2003-11-04
Tse, Young T. (Department: 2634)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C327S156000, C327S160000
Reexamination Certificate
active
06643347
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an apparatus for generating a reference clock signal from reference information in a bit stream transmitted as, for example, a sequence of MPEG2 transport packets used by digital broadcasting.
2. Description of the Related Art
In digital broadcasting, video and audio signals related to a plurality of programs are transmitted as a bit stream on a multiplexed basis. A receiver side for digital broadcasting is required to generate a reference clock signal which serves as a system clock signal.
It is known that a transmitter side for digital broadcasting generates reference information designed to enable a receiver side to generate a system clock signal, and periodically inserts the reference information into a bit stream to be transmitted. In this case, a receiver side detects the reference information in a received bit stream, and generates a system clock signal from the detected reference information. Specifically, the receiver side includes a voltage-controlled oscillator (VCO) and a phase locked loop circuit (a PLL circuit). The PLL circuit phase-locks the oscillator to the detected reference signal, thereby generating a system clock signal from the detected reference signal.
In general, there are variations in characteristic among PLL circuits. Accordingly, the above-mentioned known clock generating system requires an adjustment of an offset in a control voltage applied to the voltage-controlled oscillator. The offset adjustment increases the manufacture cost of the receiver side.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a clock signal generation apparatus which dispenses with an offset adjustment.
A first aspect of this invention provides a clock signal generation apparatus comprising first means for extracting reference information from an input digital signal; an oscillator for generating a reference clock signal having a frequency depending on a control signal; second means connected to the first means and the oscillator for generating the control signal to the oscillator in response to the reference clock signal generated by the oscillator and the reference information extracted by the first means, and for locking a phase of the reference clock signal to the reference information; a memory; third means connected to the second means for deciding whether or not the phase of the reference clock signal is successfully locked to the reference information; fourth means connected to the second means, the memory, and the third means for storing the control signal generated by the second means into the memory when the third means decides that the phase of the reference clock signal is successfully locked to the reference information; and fifth means connected to the memory, the oscillator, and the second means for selecting one of the control signal currently generated by the second means and the control signal stored in the memory, and for feeding the selected control signal to the oscillator.
A second aspect of this invention is based on the first aspect thereof, and provides a clock signal generation apparatus wherein the fifth means comprises means for feeding the control signal currently generated by the second means to the oscillator when the input signal is equal to a received digital broadcasting signal, and means for feeding the stored control signal from the memory to the oscillator when the input signal is different from a received digital broadcasting signal.
A third aspect of this invention is based on the first aspect thereof, and provides a clock signal generation apparatus further comprising sixth means connected to the fourth means for inhibiting the fourth means from storing the control signal generated by the second means into the memory when an accuracy of the reference information is lower than a given accuracy.
A fourth aspect of this invention provides a clock signal generation apparatus comprising first means for extracting reference information from an input digital signal; a first oscillator for generating a reference clock signal having a frequency depending on a control signal; second means connected to the first means and the oscillator for generating a first error signal in response to the reference clock signal generated by the first oscillator and the reference information extracted by the first means; a second oscillator for generating a basic signal having a fixed frequency; third means connected to the first oscillator and the second oscillator for generating a second error signal in response to the reference clock signal generated by the first oscillator and the basic signal generated by the second oscillator; and fourth means connected to the oscillator, the second means, and the third means for selecting one of the first error signal generated by the second means and the second error signal generated by the third means, and for feeding the selected error signal to the oscillator as the control signal; wherein the reference clock signal is phase-locked to the reference information when the fourth means feeds the first error signal to the oscillator as the control signal, and the reference clock signal is phase-locked to the basic signal when the fourth means feeds the second error signal to the oscillator as the control signal.
REFERENCES:
patent: 4511859 (1985-04-01), Dombrowski
patent: 4703520 (1987-10-01), Rozanski, Jr. et al.
patent: 4996596 (1991-02-01), Hirao et al.
patent: 5299237 (1994-03-01), Head
patent: 5424687 (1995-06-01), Fukuda
patent: 5483180 (1996-01-01), Chai et al.
patent: 5661440 (1997-08-01), Osaka
patent: 5671260 (1997-09-01), Yamauchi et al.
patent: 5703511 (1997-12-01), Okamoto
patent: 5777520 (1998-07-01), Kawakami
patent: 5841323 (1998-11-01), Fujimoto
patent: 5847614 (1998-12-01), Gilbert et al.
patent: 5917552 (1999-06-01), Van Court
patent: 5982239 (1999-11-01), Takahashi et al.
patent: 6141163 (2000-10-01), Nakamura et al.
patent: 10-11902 (1998-01-01), None
SCR, PCR (Clock Reference Value); The latest MPEG Textbook by Point Diagrammatical Method: Aug. 1, 1994: pp. 237-238 (w/Eng. translation).
Connolly Bove & Lodge & Hutz LLP
Tse Young T.
Victor Company
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