Clock signal feeding circuit

Details Clock signal feeding circuit Clock signal feeding circuit

2002-12-19

2004-09-07

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S046000, C327S141000

Reexamination Certificate

active

06788110

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock signal feeding circuit that feeds clock signals to a synchronous semiconductor logic circuit.
2. Description of the Related Art
A logic circuit of a system large-scale integrated circuit (LSI), which is used in a central processing unit (CPU) or in a digital signal processor (DSP) and the like, is typically a synchronous circuit that controls operation of each logic circuit block synchronously with common clock signals. A synchronous circuit consists of a plurality of flip-flops (FFs) that synchronize the transmitting and receiving of data between logic circuit blocks with clock signals, and a clock signal feeding circuit that feeds clock signals to these FFs.
FIG. 2A
is a circuitry diagram and
FIG. 2B
is a signal timing chart.
FIGS. 2A and 2B
illustrate a portion of a clock signal feeding circuit in a conventional logic circuit.
As shown in
FIG. 2A
, the clock signal feeding circuit feeds clock signals CKs, which have been inputted into an input terminal
3
, synchronously to a FF
1
and a FF
2
that are provided at input and output sides of a logic circuit block LB, respectively.
The clock signal feeding circuit comprises the input terminal
3
, a clock signal line
4
connected to the input terminal
3
, and delay buffers
5
and
6
. The delay buffer
5
is provided on the clock signal line
4
, downstream of a branch point
4
1
, and feeds clock signal CK
1
to a clock terminal C of the FF
1
. The delay buffer
6
is provided on the clock signal line
4
, downstream of a branch point
4
2
, and feeds clock signal CK
2
to a clock terminal C of the FF
2
. The clock signal CK
1
is fed to the FF
1
provided close to the input terminal
3
, via the branch point
4
1
and delay buffer
5
. The delay buffer
5
consists of four cascaded buffers
5
a
through
5
d
. The clock signal CK
2
is fed to the FF
2
provided away from the input terminal
3
, via the branch point
4
2
and delay buffer
6
. The delay buffer
6
consists of three cascaded buffers
6
a
through
6
c.
Each of the buffers
5
a
through
5
d
and
6
a
through
6
c
is formed from two serially-connected inverters, and is designed such that propagation delay time for each clock signal is constant. The number of the buffers inserted between the branch points
4
1
,
4
2
of the clock signal line
4
and the clock terminal C of the FF
1
and the FF
2
is selected such that the clock signals CK
1
and CK
2
are synchronized at the clock terminal C of each FF
1
and FF
2
.
The operation will be described below.
As
FIG. 2B
shows, the clock signal CK inputted at the input terminal
3
is fed to the clock terminal C of the FF
1
as the clock signal CK
1
via the clock signal line
4
and the delay buffer
5
, after a predetermined delay time. Similarly, the clock signal CK is fed to the clock terminal C of the FF
2
as the clock signal CK
2
via the clock signal line
4
and the delay buffer
6
, after a predetermined delay time. In this manner, the clock signals CK
1
and CK
2
are fed to the FF
1
and FF
2
, respectively, in a substantially synchronized manner.
A data signal DT
1
, sent from a preceding logic circuit block (not shown) to a data terminal D of the FF
1
, is latched by the FF
1
at a rise edge A of the clock signal CK
1
and outputted from an output terminal Q as a data signal DT
2
. A data signal DT
2
, outputted from the FF
1
, is fed to the logic circuit block LB where predetermined logic operations are processed. After processing time TP has elapsed, a data signal DT
3
representing the operation result is outputted and then inputted to the data terminal D of the FF
2
.
The data signal DT
3
, inputted into the FF
2
, is latched by the FF
2
at a next rise edge B of the clock signal CK
2
and outputted from an output terminal Q as a data signal DT
4
. The data signal DT
4
, outputted from the FF
2
, is fed to a subsequent logic circuit block (not shown).
The logic operation processing is conducted at each logic circuit block during each cycle of the clock signal CK, and the operation result is fed to the subsequent logic circuit block synchronously with the clock signal CK. Assuming that the cycle time of the clock signal CK is denoted by TC and the maximum processing time of the logic circuit block is denoted by TP, the margin of time TM of the operation in the logic circuit can be represented as TM=TC−TP.
Because the clock signal feeding circuit is structured such that the clock signals CK
1
, CK
2
and the like are fed to the FF
1
, FF
2
and the like synchronously, each logic circuit block can be designed simply and operation of the entire logic circuit becomes stable.
However, conventional clock signal feeding circuits have the following problems.
In each logic circuit block, data signals are inputted or outputted by clock signals that are fed synchronously in a constant cycle. Accordingly, each logic circuit block must be designed such that, even under the worst conditions within a guaranteed operating extent, the maximum processing time TP of the logic circuit block is shorter than the cycle time TC of the clock signal CK.
Reduction in operating speed of the logic circuit block is caused by variations in the operating environment, such as increases in the operating temperature, decreases in the power source voltage, and by the effect of variation in the manufacturing process. Variations in the operating environment contributing to the reduction in operating speed may include increases in gate oxide film thickness, increases in gate length, reduction in gate width, decrease in channel ion density, and the like. Logic circuits must meet the predetermined standards even if all of these operating speed reducing factors occur at the same time.
However, each of the logic circuit blocks, which altogether form the logic circuit, has a different function. The logic circuit has integrated therein both critical blocks requiring longer processing time for complex operations and simple circuits for simple operations. Therefore, the problem is that when specifications of the guaranteed operating extent are established based on the worst conditions in the critical blocks, even if the specifications in other logic circuit blocks become excessive, control of the maximum speed of the clock signal CK must be obtained.
SUMMARY OF THE INVENTION
The present invention is devised to solve the problems relating to the prior art and provide a clock signal feeding circuit that controls reduction in operating speed due to variation in conditions, and suppresses performance degradation under the worst operating conditions.
To solve the above problems, a first aspect of the present invention is a clock signal feeding circuit for feeding common clock signals to flip-flops that transmit and receive data between a plurality of logic circuit blocks, which form a semiconductor logic circuit, the clock signal feeding circuit comprising: a first delay buffer for feeding the clock signals to a first flip-flop, which passes data to a critical block with the longest processing time among those of the plurality of logic circuit blocks, the clock signals fed using at least one delay element of which variation in delay time resulting from variations in an operating environment or a manufacturing process is less than that of a critical block; and a second delay buffer for feeding the clock signals to a second flip-flop, which receives data from the critical block, the clock signals fed using delay elements of which variation in delay time resulting from an operating environment or a manufacturing process is substantially equal to variation in delay time of the critical block.
In a second aspect of the present invention, the first delay buffer in the first aspect includes a delay element that possesses a capacitor.
In a third aspect of the present invention, the second delay buffer in the first aspect is formed from a delay element that possesses a transistor of which gate length is substantially equal to that of the t

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