Clock signal extraction circuit

Details Clock signal extraction circuit Clock signal extraction circuit

1999-06-22

2003-04-15

Pham, Chi (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S226000, C375S375000, C375S376000, C370S229000, C370S242000

Reexamination Certificate

active

06549598

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a clock signal extraction circuit which receives serial data having clock information therein and extracts the clock information to reproduce a clock signal that is synchronized with the serial data, and more particularly, to a clock signal extraction circuit which extracts the clock information based on each edge of the serial data rather than the information contained in a synchronous signal to reproduce a clock signal.
BACKGROUND ART OF THE INVENTION
In a digital communication system, for example, a receiver has to extract clock information from the received data and regenerate a clock signal to accurately and properly utilize the received data. An example of conventional technology of such a clock signal extraction circuit is shown in FIG.
3
. An Example of
FIG. 3
is basically a PLL (phase lock loop) oscillation circuit.
FIGS. 4A-4H
are timing charts showing the operation of the clock signal extraction circuit of FIG.
3
.
In the timing chart of
FIG. 4
, it is assumed that the transmitted data (
FIG. 4C
) has an RZ (return-to-zero) waveform which is produced by transmitter data (
FIG. 4A
) and a transmitter clock signal (FIG.
4
B). It is also assumed that the clock signal extraction circuit of
FIG. 3
is to extract the clock information from the synchronous signal S
ync
of period 3T in the serial data where a time period T is a time length of one clock cycle.
Thus, the receiver receives the transmitted serial data D
1
from which the clock signal extraction circuit of
FIG. 3
is to produce a clock signal CK
1
of FIG.
4
H. In the example of
FIG. 3
, the clock signal extraction circuit comprises a voltage controlled oscillator (VCO)
60
, a frequency divider
62
, a phase comparator
70
, a low pass filter (LPF)
72
, an edge detector
50
, a single period (T) filter
52
, and a double period (2T) filter
54
. A negative feedback loop, i.e., a PLL is formed by returning the output of the phase comparator
70
to the VCO
60
through the low pass filter
72
.
The VCO
60
is a voltage-controlled oscillator which oscillates at a frequency close to the frequency of the clock signal in the transmitter that is to be reproduced. The frequency of the voltage controlled oscillator can be varied by regulating the voltage provided thereto. As is well known in the art, such a voltage controlled oscillator is formed by various manners including an LC oscillator in which a variable capacitor diode is incorporated, a voltage controlled crystal oscillator having a fine tuning capability, and the like.
The phase comparator
70
produces a control signal
71
whose voltage indicates the phase difference between the two input signals. The control signal
71
is filtered (averaged) by the LPF
72
so that the VCO
60
receives a control signal
73
from the LPF
72
. The oscillation frequency of the VCO
60
is controlled by the voltage of the control signal
73
to decrease the phase difference at input of the phase comparator, i.e. phase lock the VCO
60
. As is well known in the art, the LPF
72
defines loop characteristics of the PLL circuit such as a loop gain, a loop band with and a pull-in range. In the foregoing arrangement, the clock signal is extracted and reproduced by the PLL circuit as a clock signal CK
1
at the output of the VCO
60
.
The edge detector
50
receives the coded serial data D
1
shown in
FIG. 4C
, and converts the front (leading) and back (trailing) edges of the received data into a pulse signal D
2
shown in FIG.
4
D. The single period filter
52
receives the pulse signal D
2
from the edge detector
50
and removes the pulses having a fundamental time period T. Thus, the output of the single period filter
52
is a remaining pulse signal D
3
shown in FIG.
4
E. The double period filter
54
receives the pulse signal D
3
from the single period filter
52
and removes the pulses having the time period 2T which is two times of the fundamental period T. Thus, at the output of the double period filter
54
, a remaining pulse signal D
4
shown in
FIG. 4F
is produced which includes the synchronous signal having the clock information showing the time period 3T.
Based on the synchronous signal having the period 3T, the clock signal extraction circuit of
FIG. 3
extracts the clock information of the fundamental time period T and generates the clock signal CK
1
having the time period T. The synchronous signal D
4
is provided to the input of the phase comparator
70
from the double period filter
54
. At another input, the phase comparator
70
receives an output signal CK
2
from the frequency divider
62
.
In this case, the frequency divider
62
divides the clock signal CK
1
from the VCO
60
into three so that the output signal CK
2
has a time period of 3T to be synchronized with the synchronous signal S
ync
having the period 3T from the double period filter
54
. As noted above, the PLL circuit operates to minimize the phase difference between the two input signals of the phase comparator
70
by regulating the oscillation frequency (phase) of the VCO
60
. In this manner, the clock signal CK
1
is extracted and reproduced at the output of the VCO
60
.
In the foregoing conventional clock signal extraction circuit of
FIG. 3
, since the phase comparator
70
compares the phase of the pulse signal D
4
, which is the synchronous signal S
ync
from the double period filter
54
with the phase of the divided clock signal CK
2
, it involves the following disadvantages. First, a relatively complex circuit is necessary which includes the edge detector
50
, the single period filter
52
, and double period filter
54
. Thus, it is not appropriate to decrease the size and cost of the clock extraction circuit.
Second, the phase comparison is performed only on the synchronous signal S
ync
because the pulse signal D
4
from the double period filter
54
is provided to the input of the phase comparator
70
. Thus, if the pulse signal D
4
involves relatively large jitters or phase fluctuations, the clock signal CK
1
reproduced PLL circuit may not have sufficient signal quality even when the LPF (low pass filter)
72
is properly adjusted.
Moreover, the division ratio of the frequency divider
62
must be known in advance to accommodate the difference in the time periods between the clock signal to be generated and the synchronous signal received. Further, the serial data needs to include the pulse signal D
4
including the synchronous signal that can be compared with the output of the voltage controlled oscillator in the PLL circuit. As noted above, the clock signal extraction circuit in the conventional technology has several drawbacks in the practical use.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a clock signal extraction circuit that can compare phase of the voltage controlled oscillator output with each edge of the serial data having clock information.
It is another object of the present invention to provide a clock signal extraction circuit which is capable of achieving a high stability operation in the clock extraction and reproduction process by increasing a phase comparator gain of the phase lock loop.
It is a further object of the present invention to provide a clock signal extraction circuit which is capable of achieving a high signal-to-noise ratio so that the produced clock signal is not affected by noise superimposed on the received data.
It is a further object of the present invention to provide a clock signal extraction circuit which is formed with a relatively simple structure, thereby achieving a low cost and small size.
In the present invention, the clock signal extraction circuit is comprised of an input terminal for receiving serial data having time periods each of which is an integer multiple of a fundamental time period of a clock signal to be reproduced, a delay element for providing a predetermined delay time to the serial data from the input terminal, a voltage controlled oscillator whose oscillation frequency is regulated by a contr

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