Clock signal-distribution network for an integrated circuit

Details Clock signal-distribution network for an integrated circuit Clock signal-distribution network for an integrated circuit

2006-12-05

2006-12-05

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Significant integrated structure, layout, or layout...

C326S037000, C326S041000, C326S093000

Reexamination Certificate

active

07145362

ABSTRACT:
Apparatus for signal distribution, and more particularly to a clock-distribution network in an integrated circuit, is described. A programmable logic device300includes an input buffer (814, 824) and an input signal distribution buffer (369) coupled to the input buffer (814, 824). The input signal distribution buffer (369) is configured to distribute a clock signal (902) within an input/output block clock region (304A,304B). Signal lines (371UD) extend to at least one other input signal distribution buffer (369).

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