Clock signal distribution circuit of tree structure with minimiz

Details Clock signal distribution circuit of tree structure with minimiz Clock signal distribution circuit of tree structure with minimiz

1996-06-12

1999-07-13

Callahan, Timothy P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326101, 327295, 327297, H03K 19003

Patent

active

059231882

ABSTRACT:
Letting p be a definite integer, q be a varying integer from 1 to p, r be an arbitrary integer such that 1.ltoreq.r.ltoreq.p, and s be a varying integer from 2 to 2p+1, among a total of 2p+1 fan-like stages each having fan-out outputs thereof equalized to each other in load and number of associated fan-like stages, a respective 2q-th one comprises branch circuits each composed of one of a pair of logic gates, a 2r+1-th one comprises branch circuits each composed of a multi-input logic gate, a respective 2q-1-th one excepting the 2r+1-th one comprises branch circuits of which any one is composed of the other of the pair of logic gates, and a respective s-th one comprises branch circuits each respectively arranged within a cell layout region therefor and connected to an s+1-th stage at a vicinal location to a barycenter of the cell layout region to repeat a fan-out output of an s-1-th fan-like stage, as it is a clock signal distributed thereto.

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