Clock signal distribution circuit

Details Clock signal distribution circuit Clock signal distribution circuit

2002-09-17

2004-02-24

Cho, James H (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S101000, C327S295000

Reexamination Certificate

active

06696863

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit for distributing a clock signal to a plurality of circuits constituting a semiconductor device.
2. Description of the Related Art
A device constituted by LSI (Large Scale Integrated circuit), etc. operates synchronously with a clock signal. Specifically, a clock signal is distributed to a plurality of circuit elements constituting the device. The plurality of circuit elements operates in accordance with the distributed clock signal.
At this time, if the lengths of wirings connecting the distributor of the clock signal and the plurality of circuit elements are not uniform, there might be caused a difference between periods of time for the clock signal to reach each of the plurality of circuit elements. If the difference is too large, timings at which signals to be processed are input or output to or from the respective circuit elements might not be coincident, resulting in that the device incorrectly functions.
A technique for preventing occurrence of a difference in time for a clock signal to reach (clock skew) is disclosed in Unexamined Japanese Patent Application KOKAI Publication No. H11-175184.
The first technique disclosed in this publication is for distributing a clock signal using an H-shaped clock wiring.
Specifically, as shown in
FIG. 9A
, a first driver
11
is placed in the center of a chip. A clock wiring
14
having an H shape is formed to have its center at the first driver
11
. Four second drivers
12
are connected to the tips of the H-shaped clock wiring
14
. Four H-shaped clock wirings
15
are formed to have their centers at the four second drivers
12
, respectively. Sixteen third drivers
13
are connected to the tips of the four H-shaped clock wirings
15
.
A clock signal is supplied from the first driver
11
through the four second drivers
12
to the sixteen third drivers
13
, from which the clock signal is supplied to a plurality of circuit elements.
The second technique disclosed in this publication is for distributing a clock signal using an H-shaped clock wiring and a meshed wiring.
Specifically, as shown in
FIG. 9B
, a first driver
11
and four second drivers
12
are connected to each other by an H-shaped clock wiring
14
, likewise the above. The four second drivers
12
are connected to sixteen third drivers
13
by a meshed wiring
21
.
Likewise the case in
FIG. 9A
, a clock signal is supplied from the first driver
11
through the four second drivers
12
to the sixteen third drivers
13
, and the clock signal is supplied from the sixteen third drivers
13
to a plurality of circuit elements.
The above described first technique only uses an H-shaped clock wiring. Therefore, positions and number for providing drivers (buffers) are limited. In this case, in order to avoid occurrence of a clock skew, it is necessary to arrange the plurality of circuit elements in correspondence with the positions of the third drivers
13
. In other words, the positions for arranging the plurality of circuit elements are limited.
According to the second technique described above, a clock signal is supplied from the four second drivers
12
to the meshed wiring. Therefore, time for the clock signal to reach each intersection on the meshed wiring is varied in accordance with distance from the second drivers
12
. In this case, the positions for arranging the third drivers
13
are limited in order to avoid occurrence of a clock skew. As a result, the positions for arranging the plurality of circuit elements are also limited.
Further, according to the structure shown in
FIG. 9B
, if a part is removed from the meshed wiring, load which is imposed on the four second drivers
12
becomes non-uniform. This non-uniformity of load may be the cause of occurrence of a clock skew. Therefore, any part of the meshed wiring shown in
FIG. 9B
should not be removed. As a result, positions for arranging macros such as a CPU (Central Processing Unit), a memory, etc. are limited.
The disclosure of Unexamined Japanese Patent Application KOKAI Publication No. H11-175184 is incorporated herein by reference.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a clock signal distribution circuit which is capable of preventing occurrence of a clock skew without limiting arrangement of circuit elements constituting a device.
To achieve the above object, a clock signal distribution circuit according to the present invention distributes an externally supplied clock signal to a plurality of circuits, and comprises:
a tree wiring having wiring routes branched like a tree;
a mesh wiring having meshed wiring routes;
a plurality of first clock buffers which are connected to terminals of the tree wiring, and supply a clock signal supplied thereto from outside through the tree wiring, to the mesh wiring; and
a plurality of second clock buffers which are connected to the mesh wiring, and supply the clock signal supplied thereto from the plurality of first clock buffers through the mesh wiring, to the plurality of circuits,
wherein the plurality of first clock buffers are connected to intersections which exist on the wiring routes of the mesh wiring in one to one correspondence.
According to this invention, it is possible to prevent occurrence of a clock skew without limiting arrangement of circuit elements constituting a device.
The mesh wiring may protrude from intersections thereof which face toward outside by a predetermined length, so that load to be imposed on the plurality of first clock buffers becomes uniform.
The mesh wiring may be constituted by a plurality of horizontal wirings arranged in parallel with one another at predetermined intervals, and a plurality of vertical wirings arranged in parallel with one another at predetermined intervals and perpendicularly to the horizontal wirings.
Ends of the plurality of horizontal wirings and ends of the plurality of vertical wirings may protrude from closest intersections by a length corresponding to a half of a mesh pitch.
A part of the mesh wiring may be removed, where the part corresponds to a region for arranging a macro to be arranged within an area in which the mesh wiring is formed.
The mesh wiring may protrude from intersections thereof which face toward the removed part by a predetermined length, so that load to be imposed on the plurality of first clock buffer becomes uniform.
The mesh wiring may be constituted by a plurality of horizontal wirings arranged in parallel with one another at predetermined intervals, and a plurality of vertical wirings arranged in parallel with one another at predetermined intervals and perpendicularly to the horizontal wirings.
In neighborhood of the removed part of the mesh wiring, ends of the plurality of horizontal wirings and ends of the plurality of vertical wirings may protrude from closest intersections by a length corresponding to a half of a mesh pitch.
Same number of the plurality of second clock buffers may be provided to each of a plurality of regions enclosed by the wiring routes of the mesh wiring.
Among the plurality of second clock buffers, a second clock buffer, to which no target circuit of supplying the clock signal is connected, may function as a dummy buffer in order to keep load to be imposed on the plurality of first clock buffers uniform.
The plurality of second clock buffers may be connected between intersections of the mesh wiring.
The tree wiring comprises at least one branching point at which a wiring route is branched into three routes.
The wiring routes of the tree wiring may be designed so that an externally supplied clock signal reaches the plurality of first clock buffers substantially at a same time.
Each of branching points of the tree wiring may have a third clock buffer which outputs a clock signal which is synchronous with a clock signal supplied thereto.
The third clock buffer which is connected to a first branching point among the branching points of the tree wiring may be arranged outside of an area in which the mesh wiring

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