Clock signal distributing circuit

Details Clock signal distributing circuit Clock signal distributing circuit

1997-03-21

1999-08-31

Heckler, Thomas M.

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Correction for skew, phase, or rate

G06F 110

Patent

active

059448369

ABSTRACT:
The invention provides a clock signal distributing circuit wherein the position at which the buffer section is disposed is determined from the positions and characteristics of the clock signal input section and the load section and the characteristics of the buffer section and the wiring section, and wirings are made through the clock signal input section, one or more stage buffer sections, and the load section, so that the signal transmission delay time as well as the skew of clock signals can be adjusted.

REFERENCES:
patent: 5502819 (1996-03-01), Aldrich et al.
patent: 5586307 (1996-12-01), Wong et al.
patent: 5625805 (1997-04-01), Fenwick et al.
patent: 5628000 (1997-05-01), Kashiyama et al.
patent: 5696951 (1997-12-01), Miller
patent: 5712579 (1998-01-01), Duong et al.
patent: 5732249 (1998-03-01), Masuda et al.

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