Clock selection for processing audio data

Details Clock selection for processing audio data Clock selection for processing audio data

1998-11-03

2002-07-16

Heckler, Thomas M. (Department: 2185)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Reexamination Certificate

active

06421785

ABSTRACT:

BACKGROUND
The invention relates generally to the field of audio data processing and, more particularly, to the automatic and dynamic selection of a clock frequency for processing audio data.
The International Electrotechnical Commission 958 (IEC-958) standard describes a serial, unidirectional, self-clocking interface (e.g., a data format and transport protocol) for the interconnection of digital audio equipment. A consumer version of the IEC-958 standard is commonly referred to as the Sony, Philips Digital Interface Format (SPDIF) interface. (International Electrotechnical Commission publication 60958-3 Ed. 1.0 entitled “Digital audio interface—Part 3: Consumer applications.”)
The SPDIF protocol defines a serial data stream comprising sub-frames, frames, and blocks. As shown in
FIG. 1
, there are 2 sub-frames (e.g.,
100
and
102
) in a frame (e.g.
104
) and
192
frames in a block (e.g.,
106
). Each sub-frame (e.g., sub-frame
100
) comprises
32
time slots. Time slots
0
through
3
may be used to encode preamble
108
information. Time slots
4
through
27
may be used to represent digital data
110
. (If less than 24 bits are used to represent the data, time slots
4
through
7
may be filled with zeros. If less than 20 bits are used to represent the data, the least significant bits (LSBs) may be filled with zeros.) Time slots
28
through
31
may be used to encode ancillary information
112
. For example: time slot
28
may be used to encode a data sample validity flag; time slot
29
may be used to encode user information; time slot
30
may encode channel status information; and time slot
31
may encode a parity indication.
If the information being transmitted in accordance with the SPDIF protocol is stereo data, such as linear pulse code modulated (LPCM) data, each frame may be used to time multiplex audio channel data. As shown in
FIG. 2.
, sub-frame
200
may be used to encode channel-
1
data
202
(left channel data, for example), and sub-frame
204
may be used to encode channel-
2
data
206
(right channel data for example). Each sub-frame also has its associated preamble (
208
and
210
) and ancillary (
212
and
214
) fields.
If the information being transmitted is multi-channel audio data, it may be divided into a discrete number of SPDIF frames and transmitted. For example, if the audio data is AC-3 data, it may be formatted as a sequence of 16 bit words and transmitted as a continuous burst of 8 SPDIF blocks (1536 SPDIF frames). (Advanced Television Systems Committee publication A/52 entitled “Digital Audio Compression (AC-3) Standard,” December 1995.)
As shown in
FIG. 3
, each AC-3 burst
300
(referred to as an AC-3 sync frame) includes a 64 bit preamble
302
comprising a synchronization code, an indicator of the burst length, and information about the type of data contained in the burst. Audio data (AB
0
-AB
5
)
304
,
306
,
308
,
310
,
312
, and
314
follows preamble
302
. Tail field
316
follows audio data AB
5
314
and may include error correction information. In general, AC-3 sync frame boundaries occur at a frequency of once every 1536 SPDIF/IEC-958 frames.
The SPDIF standard may be embodied in a SPDIF module as shown in FIG.
4
. Module
400
may include controller
402
, formatter
404
, and output circuit
406
. Controller
402
provides a mechanism through which an application program
408
may communicate with module
400
(e.g., to provide and/or receive audio data). Controller
402
also provides a mechanism through which module
400
interacts with memory
410
. The memory mechanism is typically a direct memory access (DMA) interface to module
400
's host computer system (not shown). Formatter
404
takes unformatted audio data and places it into SPDIF format as described above and illustrated in
FIGS. 1 through 3
. Output circuit
406
takes formatted SPDIF frames from formatter
404
and an appropriate input clock signal
412
, and transmits a serial data stream to a target device. The IEC-958 standard currently allows for three clocking, or sampling frequencies: 48.0 KHz; 44.1 KHz; and 32.0 KHz. That is, the audio data transmitted in a SPDIF block may have an associated sampling frequency of 48.0 KHz, 44.1 KHz, or 32.0 KHz. Thus, input clock signal
412
is one of these clocking frequencies, or a multiple (typically 64 or 128 times) of one of these three clocking frequencies.
SUMMARY
In one embodiment, a circuit provides a register to receive indication of a data sampling frequency, a selection circuit operatively coupled to the register, the indicated data sampling frequency selecting one of a plurality of signals provided to the selection circuit, and a modification circuit to modify the selected signal based at least in part on the indicated sampling frequency. In another embodiment, the modified selected signal may be provided, as a clock signal, to an audio processing circuit.
In yet another embodiment, a method to generate a clock signal is provided. The method includes receiving a signal indicating a data sampling frequency, selecting one clock signal from a plurality of input clock signals based on the received data sampling frequency indication, and modifying the selected clock signal, based on the indicated sampling frequency, to generate an output clock signal. In still another embodiment, the output clock signal may be used, for example, as a clock signal for an audio processing circuit. The method may be stored in any media that is readable and executable by a programmable control device.
In yet another embodiment, a computer system comprises a bus, a host processor operatively coupled to the bus, an audio processing circuit operatively coupled to the bus, and a clock circuit operatively coupled to the audio processing circuit, the clock circuit having a register to receive indication of a data sampling frequency from the audio processing circuit, a selection circuit operatively coupled to the register, the indicated data sampling frequency selecting one of a plurality of signals provided to the selection circuit, and a modification circuit to modify the selected signal based on the indicated sampling frequency.


REFERENCES:
patent: 4430722 (1984-02-01), Massen et al.
patent: 4550292 (1985-10-01), Smith
patent: 4852124 (1989-07-01), Raucci
patent: 4974082 (1990-11-01), Heitmann
patent: 5218363 (1993-06-01), LeCroy, Jr. et al.

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