Clock reshaping

Details Clock reshaping Clock reshaping

2001-02-27

2002-12-24

Le, Don Phu (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S029000

Reexamination Certificate

active

06498512

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to clock reshaping.
Digital electronics systems, such as computers, must move data among their component devices at increasing rates to take full advantage of the higher speeds at which these component devices operate. For example, a computer may include one or more processors that operate at frequencies of a gigahertz (GHz) or more. The data throughput of these processors outstrips the data delivery bandwidth of conventional systems by significant margins.
The digital bandwidth (BW) of a communication channel may be represented as:
BW=F
s
N
s
.
Here, F
s
is the frequency at which symbols are transmitted on a channel and N
s
is the number of bits transmitted per symbol per clock cycle (“symbol density”). Channel refers to a basic unit of communication, for example a board trace in single ended signaling or the two complementary traces in differential signaling.
Conventional strategies for improving BW have focused on increasing one or both of the parameters F
s
and N
s
. However, these parameters cannot be increased without limit. For example, a bus trace behaves like a transmission line for frequencies at which the signal wavelength becomes comparable to the bus dimensions. In this high frequency regime, the electrical properties of the bus must be carefully managed. This is particularly true in standard multi-drop bus systems, which include three or more devices that are electrically connected to each bus trace through parallel stubs.
Practical BW limits are also created by interactions between the BW parameters, particularly at high frequencies. For example, the greater self-induced noise associated with high frequency signaling limits the reliability with which signals can be resolved. This limits the opportunity for employing higher symbol densities.
Modulation techniques have been employed in some digital systems to encode multiple bits in each transmitted symbol, thereby increasing N
s
. Use of these techniques has been largely limited to point-to-point communication systems, particularly at high signaling frequencies. Because of their higher data densities, encoded symbols can be reliably resolved only in relatively low noise environments. Transmission line effects limit the use of modulation in high frequency communications, especially in multi-drop environments.
The shape of clock pulses used to control the modulation of a transmitted symbol by a modulator circuit may have to be carefully controlled.


REFERENCES:
patent: 5180937 (1993-01-01), Laird et al.
patent: 5455530 (1995-10-01), Huppenthal et al.
patent: 5920704 (1999-07-01), Olnowich et al.
patent: 5923621 (1999-07-01), Kanekal et al.
patent: 6060922 (2000-05-01), Chow et al.
patent: 6160754 (2000-12-01), Suh

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