Clock regenerator

Details Clock regenerator Clock regenerator

1986-05-06

1987-09-01

Griffin, Robert L.

Pulse or digital communications

Repeaters

Testing

375120, 331 1A, 328 63, H04L 2560

Patent

active

046913270

ABSTRACT:
A clock regenerator is designed as a phase locked loop (PLL) and comprises a phase detector (DET) which compares the phase of the input signal (Sp) with that of the output signal (Sa), the frequency of the phase detector being approximately N times smaller than the oscillator frequency. In the phase detector (DET), there are obtained from a regenerated output signal (Sa) two signals delayed by L/N periods, wherein L is a small integer, in order to form therefrom a pulse window comprising at least three zones. The clock regenerator comprises a loop filter (FIL) with a counter, the status of which is recorded in a logic circuit which controls a programmable divisor (DIV) in such a way that when the edges of the input pulse (Sp) fall in the central most zone, the counter counts toward zero and no correction is brought about.

REFERENCES:
patent: 3936762 (1976-02-01), Cox, Jr. et al.
patent: 4151485 (1979-04-01), La Fratta
patent: 4227251 (1980-10-01), Kazama et al.
patent: 4280099 (1981-07-01), Rattlingourd
patent: 4327356 (1982-04-01), Gilliland
patent: 4400817 (1983-08-01), Sumner
patent: 4569064 (1986-02-01), Collin et al.
patent: 4590602 (1986-05-01), Wolaver
Cessna & Levy, "Phase Noise and Transient Times for a Binary Quantized Digital Phase-Locked Loop in White Gaussian Noise", IEEE Trans. on Comm. vol. COM-20, No. 2, Apr. 1972, pp. 94-104.

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