Clock regeneration circuit

Details Clock regeneration circuit Clock regeneration circuit

1996-01-16

1996-11-05

Westin, Edward P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

327166, 327291, H03K 1900

Patent

active

055721494

ABSTRACT:
A clock regeneration circuit capable of obtaining clocks each having an arbitrary duty. The clock regeneration circuit comprises a first D-type flip-flop having a clock terminal for receiving an input clock signal from an input terminal, and a data input terminal for receiving data of an H level, a second D-type flip-flop having a clock terminal for receiving the input clock signal from the input terminal, and a data input terminal for receiving data of an H level, a first delay circuit which receives an output from an output terminal of the first D-type flip-flop and outputs an output thereof to the reset terminal of the first D-type flip-flop, and a second delay circuit which receives the output from an output terminal of the first D-type flip-flop and outputs an output to a reset terminal of the second D-type flip-flop, wherein an output clock signal is outputted from an output terminal of the second D-type flip-flop to an output terminal.

REFERENCES:
patent: 4972161 (1990-11-01), Davies
patent: 5059818 (1991-10-01), Witt
patent: 5418822 (1995-05-01), Schlachter et al.

Affiliated with

Also associated with

Rating

Clock regeneration circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock regeneration circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock regeneration circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2017300