Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
2000-10-06
2004-05-18
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C713S500000, C713S501000
Reexamination Certificate
active
06738922
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to a clock recovery unit, and more particularly, to a method and apparatus for recovering a clock signal from a transmitted data signal using a clock recovery unit (CRU) that includes a frequency detector.
Data transmission systems generally transmit clocked data. Receiver units generally must determine the clock, both in frequency and in phase, used to generate the clocked data. A clock recovery unit (CRU) based on a phase locked loop (PLL) circuit is typically used to recover a corresponding clock signal from a transmitted data signal. In a PLL circuit, a feedback loop is generally used to adjust a variable clock signal output of a voltage-controlled oscillator (VCO) until the variable clock signal aligns with the transmitted data signal. The variable clock signal aligned with the transmitted data signal is used as a recovered clock signal that corresponds to the transmitted data signal. In other words, the output of the VCO is the recovered clock signal.
The PLL circuit typically includes a phase detector to detect a phase difference between the transmitted data signal and the variable clock signal. The phase difference is used to adjust the output frequency of the VCO to align the variable clock signal to the transmitted data signal, both in phase and in frequency.
Since the recovered clock signal behaves in a periodic manner, when the phase difference between the transmitted data signal and the recovered clock signal becomes too large, the output signal of the phase detector may “wrap around” to a new value. For example, if the phase detector is capable of generating a phase difference signal representing a phase difference in the range of −180 degrees to +180 degrees, the output signal of the phase detector will increase as the phase difference between the transmitted data signal and the recovered clock signal increases up to +180 degrees.
When the phase difference increases further to more than +180 degrees, the phase detector is typically unable to generate a phase difference signal to represent a phase difference of more than +180 degrees. Instead, a phase wrapping occurs at approximately +180 degrees, and the phase detector generates a phase difference signal that represents a phase difference of approximately −180 degrees. This phase wrapping causes a problem of phase ambiguity around the maximum and minimum phase differences of +180 degrees and −180 degrees, respectively.
The phase wrapping generally does not present a problem once the PLL circuit is locked to the transmitted data signal. This is because the PLL circuit generally holds the phase difference to a very small value close to zero degree, in which case phase wrapping typically does not occur. However, the phase wrapping may present a serious problem before the PLL circuit locks. The PLL circuit may not even be able to lock because of the phase wrapping problem. When phase wrapping occurs, the phase difference signal generated by the phase detector may switch back and forth between nearly maximum and nearly minimum values, and the phase locked loop may not be able to adjust the VCO to generate the variable clock signal with correct frequency.
One solution is use of a narrow band voltage controlled oscillator (VCO) that has a tuning range of approximately 1% or less. This limitation in the tuning range typically limits the frequency difference between a data signal and an oscillation frequency of the VCO to be very small. With such small frequency differences, phase wrapping typically does not occur very often, and the PLL circuit generally is able to lock. While this solution is typically effective when a narrow band VCO is used, it is usually impractical since the tuning range of a VCO is generally much larger than 1% of the frequency.
Therefore, a need exists for a clock recovery unit that can solve the wrap around problem while its VCO tuning range is sufficiently large as to be practical for applications using IC designs.
SUMMARY OF THE INVENTION
The present invention provides a clock recovery unit (CRU) for recovering a corresponding clock signal from a transmitted data signal. The CRU includes a frequency detection circuit and a phase locked loop (PLL) circuit to detect phase and frequency differences between a reference clock signal and a variable clock signal, and to adjust the variable clock frequency to recover a clock signal that corresponds to the transmitted data signal.
In one embodiment the present invention comprises a clock recovery unit. The clock recovery unit includes a phase locked loop to receive a transmitted data signal and to generate an output clock signal. The clock recovery unit further comprises a frequency detection circuit to receive the output clock signal and a reference clock signal, and to generate an output signal to provide to the phase locked loop, with the phase locked loop using the output signal to establish a phase lock between the transmitted data signal and the output clock signal. In a further embodiment, the clock recovery unit includes a phase difference signal which is proportional to the phase difference between a reference clock signal and a shifted output clock signal, with a frequency detection circuit including a glitch suppressor to suppress the phase difference signal when the width of the phase difference signal is substantially narrow.
These and other aspects of the present invention may be more fully understood through reference to the following detailed description with reference to the accompanying drawings.
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Coe Tim
Warwar Greg
Lee Thomas
Vitesse Semiconductor Corporation
Yanchus, III Paul
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